A Generic Architecture for On-Chip Packet-Switched Interconnections
This paper presents an architectural study of a scalable system-level interconnection template. We explain why the shared bus, which is today’s dominant template, will not meet the performance requirements of tomorrow’s systems. We present an alternative interconnection in the form of switching networks. This technology originates in parallel computing, but is also well suited for heterogeneous communication between embedded processors and addresses many of the deep submicron integration issues. We discuss the necessity and the ways to provide high-level services on top of the bare network packet protocol, such as dataflow and address-space communication services. Eventually we present our first results on the cost/performance assessment of an integrated switching network.
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