Skip to main content

Abstract

We are witnessing a growing interest in Networks on Chips (NoC) that is related to the evolution of integrated circuit technology and to the growing requirements in performance and portability of electronic systems. Current integrated circuits contain several processing cores, and even relatively simple systems, such as cellular telephones, behave as multiprocessors. Moreover, many electronic systems consist of heterogeneous components and they require efficient on-chip communication. In the last few years, multiprocessing platforms have been developed to address high performance computation, such as image rendering. Examples are Sony’s emotion engine [OKA] and IBM’s cell chip [PHAM] where on-chip communication efficiency is key to the overall system performance.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. G. De Micheli and L. Benini, Networks on Chips, Morgan Kaufmann, 2006.

    Google Scholar 

  2. W. Dally and C. Seitz, The Torus Routing Chip, Distributed Processing, Vol 1.pp. 187-196, 1996.

    Article  Google Scholar 

  3. W. Dally and B. Towles, Route Packets, Not Wires: On-Chip Interconnection Networks, Proceedings of the 38th Design Automation Conference, pp. 684–689, 2001.

    Google Scholar 

  4. M. Dall’Osso, G. Biccari, L. Giovannini, D. Bertozzi and L. Benini, Xpipes: A Latency. Insensitive Parameterized Network-on-Chip Architecture for Multi-Processor SoCs, International Conference on Computer Design, pp. 536–539, 2003.

    Google Scholar 

  5. P. Guerrier and A. Greiner, A Generic Architecture for On-Chip Packet-Switched Interconnections, DATE- Proceedings of the Design Automation and Test in Europe Conference, pp. 250–256, 2000.

    Google Scholar 

  6. J. Hu and R. Marculescu, Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures, DATE- Proceedings of the Design and Test Europe Conference, pp. 10688–10693, 2003.

    Google Scholar 

  7. A. Jalabert, S. Murali, L. Benini and G. De Micheli, xpipesCompiler: a tool for instantiating application specific Networks on Chips, DATE- Proceedings of the Design and Test Europe Conference, pp. 884–889, 2004.

    Google Scholar 

  8. S. Mahadevan, F. Angiolini, M. Storgaard, R.G. Olsen, J. Sparsø and J. Madsen, A Network Traffic Generator Model for fast Network on-Chip Simulation, DATE- Proceedings of the Design and Test Europe Conference, pp. 780–785, 2005.

    Google Scholar 

  9. S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli and L. Raffo, Designing Application-specific Networks on Chips with Floorplan Information, International Conference on Computer Aided Design, pp. 355–362, 2006.

    Google Scholar 

  10. M. Oka and M. Suzuoki, Designing and Programming the Emotion Engine, IEEE Micro, Vol. 19, No. 6, 20–28, Nov.–Dec, 1999.

    Article  Google Scholar 

  11. A. Pullini, F. Angiolini, P. Meloni, D. Atienza, S. Murali, L. Raffo, G. De Micheli and L. Benini, NoC Design and Implementation in 65nm Technology, International Symposium on Networks on Chips, pp. 273–282, 2007.

    Google Scholar 

  12. E. Rijpkema, K. Goossens, A. Rădulescu, J. Dielissen, J. van Meerbergen, P. Wielage and E Waterlander, Trade Offs in the Design of a Router with Both Guaranteed and Best Effort Services for Networks on Chips, DATE- Proceedings of the Design and Test Europe Conference, pp. 10350–10355, 2003.

    Google Scholar 

  13. T. Theis, The future of Interconnection Technology, IBM Journal of Research and Development, Vol. 44, No. 3, 379–390, May 2000.

    Article  Google Scholar 

  14. S. Vangal et al., An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. International Solid-State Circuits Conference, pp. 98–99, 2007.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2008 Springer

About this chapter

Cite this chapter

De Micheli, G. (2008). Networks on Chips. In: Lauwereins, R., Madsen, J. (eds) Design, Automation, and Test in Europe. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6488-3_8

Download citation

  • DOI: https://doi.org/10.1007/978-1-4020-6488-3_8

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-1-4020-6487-6

  • Online ISBN: 978-1-4020-6488-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics