Abstract
In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.
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References
A. Benso, S. Cataldo, S. Chiusano, P. Prinetto, Y. Zorian, A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures, JETTA, Vol. 16.3, 179–184, June 2000.
Y. Zorian, A Distributed BIST Control Scheme for Complex VLSI Devices, Proc. VLSI Test Symp., 4–9, April 1993.
M. Garg, A. Basu, T.C. Wilson, D.K. Banerji, J.C. Majithia, A New Test Scheduling Algorithm for VLSI Systems, Proc. Symp. on VLSI Design, pp. 148–153, November 1999.
K. Chakrabarty, Test Scheduling for Core-Based Systems, Proc. Int. Conf on CAD, pp. 391–394, January 1991.
R. Chou, K. Saluja, V. Agrawal, Scheduling Tests for VLSI Systems Under Power Constraints, IEEE Trans. VLSI Systems, Vol. 5, No. 2, 175–185, June 1997.
V. Muresan et al., A Comparison of Classical Scheduling Approaches in Power-Constrained Block-Test Scheduling, Proc. Int. Test Conf., pp. 882–891, 3–5 October 2000.
H. Bleeker et al. Boundary-Scan Test: A Practical Approach, Kluwer Academic. ISBN 0–7923-9296–5, 1993.
E.J. Marinissen et al. A Structured and Scalable Mechanism for Test Access to Embedded Reusable Cores, Proc. International Test Conf., pp. 284–293, October 18–23, 1998.
IEEE P1500 Web site. http://grouper.ieee.org/groups/1500/.
M. Sugihara, H. Date, H. Yasuura, A Test Methodology for Core-Based System LSIs, IEICE Trans. Fund. Vol. E81-A, No. 12, 2640–2645, December 1998.
J. Aerts, E. J. Marinissen, Scan Chain Design for Test Time Reduction in Core-Based ICs, Proc. International Test Conference, pp. 448–457, 1998.
G. Hetherington et al. Logic BIST for Large Industrial Designs: Real Issues and Case Studies, Proc. International Test Conference, pp. 358–367, 1999.
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Larsson, E., Peng, Z. (2008). An Integrated System-on-Chip Test Framework. In: Lauwereins, R., Madsen, J. (eds) Design, Automation, and Test in Europe. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6488-3_32
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DOI: https://doi.org/10.1007/978-1-4020-6488-3_32
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-6487-6
Online ISBN: 978-1-4020-6488-3
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