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Address Bus Encoding Techniques for System-Level Power Optimization

  • Luca Benini
  • Giovanni De Micheli
  • Enrico Macii
  • Donatella Sciuto
  • Cristina Silvano
  • Luca Benini
  • Giovanni De Micheli
  • Enrico Macii
  • Donatella Sciuto
  • Cristina Silvano

Abstract

The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I/O interfaces can provide significant savings on the overall power budget. This paper presents innovative encoding techniques suitable for minimizing the switching activity of system-level address buses. In particular, the schemes illustrated here target the reduction of the average number of bus line transitions per clock cycle. Experimental results, conducted on address streams generated by a real microprocessor, have demonstrated the effectiveness of the proposed methods.

Keywords

Data Address Switching Activity Very Large Scale Integration Gray Code Address Stream 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer 2008

Authors and Affiliations

  • Luca Benini
  • Giovanni De Micheli
  • Enrico Macii
  • Donatella Sciuto
  • Cristina Silvano
  • Luca Benini
    • 1
  • Giovanni De Micheli
    • 2
  • Enrico Macii
    • 3
  • Donatella Sciuto
    • 4
  • Cristina Silvano
    • 3
  1. 1.Politecnico di Milano Dip. di Elettronica e Informazione MilanoITALY
  2. 2.Politecnico di Torino Dip. di Automatica e Informatica TorinoITALY
  3. 3.Stanford University Computer Systems Laboratory Stanford
  4. 4.Università di Brescia Dip. di Elettronica per l’Automazione BresciaITALY

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