Skip to main content

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

  • 1200 Accesses

This book has proposed and examined various wireless transceiver architectures and circuit structures to achieve multistandard and low-voltage compliance.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. P.-I. Mak, S.-P. U and R. P. Martins, “A 1-V Transient-Free and DC-Offset- Canceled PGA with a 17.1-MHz Constant Bandwidth over 52-dB Control Range in 0.35-µm CMOS,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 649-652, Sept. 2005.

    Google Scholar 

  2. R. G. Meyer and W. D. Mack, “A DC to 1-GHz Differential Monolithic Variable- Gain Amplifier,” IEEE Journal of Solid-State Circuits (JSSC), vol. 26, no. 11, pp. 1673-1680, Nov. 1991.

    Article  Google Scholar 

  3. R. Gomez and A. A. Abidi, “A 50-MHz CMOS Variable-Gain Amplifier for Magnetic Data Storage Systemx,” IEEE Journal of Solid-State Circuits (JSSC), vol. 27, no. 6, pp. 935-939, June 1992.

    Article  Google Scholar 

  4. R. Harjani, “A Low-Power CMOS VGA for 50Mb/s Disk Drive Read Channels,” IEEE Transactions on Circuits and Systems-II (TCAS-II), vol. 42, pp. 370-376, June 1995.

    Article  Google Scholar 

  5. J. J. F. Rijns, “CMOS Low-Distortion High-Frequency Variable-Gain Amplifier,” IEEE Journal of Solid-State Circuits (JSSC), vol. 31, no. 7, pp. 1029-1034, July 1996.

    Article  Google Scholar 

  6. P. J. G. van Lieshout and R. J. van de Plassche, “A Power-Efficient, Low-Distortion Variable Gain Amplifier Consisting of Coupled Differential Pairs,” IEEE Journal of Solid-State Circuits (JSSC), vol. 32, no. 12, pp. 2105-2110, Dec. 1997.

    Article  Google Scholar 

  7. T. Yamaji, N. Kanou and T. Itakura, “A Temperature-Stable CMOS Variable-Gain Amplifier With 80-dB Linearly Controlled Gain Range,” IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 77-80, 2001.

    Google Scholar 

  8. K.-S Nah and B.-H Park, “A 50-MHz 98-dB Dynamic-Range dB-Linear Program- mable-Gain Amplifier with 2-dB Gain Steps for 3-V Power Supply,” IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 73-76, 2001.

    Google Scholar 

  9. K. Philips and E. C. Dijkmans, “A Variable-Gain IF Amplifier with -67dBc IM3- distortion at 1.4 Vpp Output in 0.25 μm CMOS,” IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 81-82, June 2001.

    Google Scholar 

  10. C.-C. Hsu and J.-T. Wu, “A 125 MHz -86 dB IM3 Programmable-Gain Amplifier,” IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 32-35, June 2002.

    Google Scholar 

  11. T. Arai and T. Itakura, “A Baseband Gain-Controlled Amplifier with a Linear-in-dB Gain Range from 14dB to 76dB and a Fixed Corner Frequency DC Offset Canceler,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 136-137, Feb. 2003.

    Google Scholar 

  12. C.-P. Wu and H.-W. Tsao, “A 110 MHz 84 dB CMOS programmable gain amplifier with RSSI,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Digest of Technical Papers, pp. 639-642, June 2003.

    Google Scholar 

  13. I. Koudar, “Variable Gain Differential Current Feedback Amplifier,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 659-662, Oct. 2004.

    Google Scholar 

  14. B. Calvo, S. Celma and M. T. Sanz, “A High-Linear 160-MHz CMOS PGA, in Proc. European Solid-State Circuits Conference (ESSCIRC), pp. 115-118, Oct. 2004.

    Google Scholar 

  15. O. Jeon, R. M. Fox and B. A. Myers, “Analog AGC Circuitry for a CMOS WLAN Receiver,” IEEE Journal of Solid-State Circuits (JSSC), vol. 41, no. 10, pp. 2291-2300, Oct. 2006.

    Article  Google Scholar 

  16. H. Huang and E. K. F. Lee, “Design of Low-Voltage CMOS Continuous-Time Filter with On-Chip Automatic Tuning,” IEEE Journal of Solid-State Circuits (JSSC), vol. 36, no. 8, pp. 1168-1177, Aug. 2001.

    Article  Google Scholar 

  17. M. Ozgun, Y. Tsividis and G. Burra, “Dynamically Power-Optimized Channel- Select Filter for Zero-IF GSM,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 504-505, Feb. 2005.

    Google Scholar 

  18. S. Chatterjee, Y. Tsividis and P. Kinget, “A 0.5V Filter with PLL-Based Tuning in 0.18μm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 506-507, Feb. 2005.

    Google Scholar 

  19. G. Vemulapalli, P. K. Hanumolu, Y.-J. Kook and U. K. Moon, “ A 0.8-V Accurately Tuned Linear Continuous-Time Filter,” IEEE Journal of Solid-State Circuits (JSSC), vol. 40, no. 9, pp. 1972-1977, Sept. 2005.

    Article  Google Scholar 

  20. T. Ueno and T. Itakura, “A 0.9V 1.5mW Continuous-Time ΔΣ Modulator for WCDMA,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 78-79, Feb. 2004.

    Google Scholar 

  21. L. Dorrer, F. Kuttner, P. Greco and S. Derksen, “A 3mW 74dB SNR 2MHz CT ΔΣ ADC with a Tracking-ADC-Quantizer in 0.13μm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 492-493, Feb. 2005.

    Google Scholar 

  22. T. Nagai, H. Satou, H. Yamazaki and Y. Watanabe, “A 1.2V 3.5mW ΔΣ Modulator with a Passive Current Summing Network and a Variable Gain Function,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 494-495, Feb. 2005.

    Google Scholar 

  23. P. Fontaine, A. N. Mohiedin and A. Bellaouar, “A Low-Noise Low-Voltage CT ΔΣ Modulator with Digital Compensation of Excess Loop Delay,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 498-499, Feb. 2005.

    Google Scholar 

  24. A. Das, R. Hezar, R. Byrd, G. Gornez and B. Haroun, “A 4th-Order 86dB CT ΔΣ ADC with Two Amplifiers in 90nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 496-498, Feb. 2005.

    Google Scholar 

  25. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigne, E. Romani, A. Melodia and V. Mellimi, “A 14b 20mW CMOS CT ΔΣ ADC with 20MHz Signal Bandwidth and 12b ENOB,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 62-63, Feb. 2006.

    Google Scholar 

  26. K.-P. Pun, S. Chatterjee and P. Kinget, “A 0.5V 74dB SNDR 25 kHz CT ΔΣ Modulator with Return-to-Open DAC,” IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 72-73, Feb. 2006.

    Google Scholar 

  27. J. Jussila A. Pärssinen and K. Halonen, “An Analog Baseband Circuitry for a WCDMA Direct Conversion Receiver,” in Proc. European Solid-State Circuits Conference (ESSCIRC), pp. 166-169, Sept. 1999.

    Google Scholar 

  28. W. Schelmbauer, H. Pretl, L. Maurer, B. Adler, R. Weigel, R. Hagelauer and J. Fenk, “An Analog Baseband Chain for UMTS Zero-IF Receiver in a 75GHz SiGe BiCMOS Technology,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Digest of Technical Papers, pp. 267-270, June 2002.

    Google Scholar 

  29. H. Elwan, M. Younus, H. Al-Zaher and M. Ismail, “A Buffer-Based Baseband Analog Front End for CMOS Bluetooth Receivers,” IEEE Transactions on Circuits and Systems-II (TCAS-II), vol. 49, no. 8, pp. 545-554, Aug. 2002.

    Article  Google Scholar 

  30. M. Lee, I. Kwon and K. Lee, “An Integrated Low Power CMOS Baseband Analog Design for Direct Conversion Receiver,” in Proc. European Solid-State Circuits Conference (ESSCIRC), pp. 79-82, Sept. 2004.

    Google Scholar 

  31. M. Elmala, B. Carlton, R. Bishop and K. Soumyanath, “A Highly Linear Filter and VGA Chain with Novel DC-Offset Correction in 90nm Digital CMOS Process,” IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 302-303, June 2005.

    Google Scholar 

  32. P.-I. Mak, S.-P. U and R. P. Martins, “A 1V 14mW-per-Channel Flexible-IF CMOS Analog-Baseband IC for 802.11a/b/g Receivers,” IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 288-289, June 2006.

    Google Scholar 

Download references

Rights and permissions

Reprints and permissions

Copyright information

© 2007 Springer

About this chapter

Cite this chapter

(2007). Conclusions. In: Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage Wireless Transceivers. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6433-3_7

Download citation

  • DOI: https://doi.org/10.1007/978-1-4020-6433-3_7

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-1-4020-6432-6

  • Online ISBN: 978-1-4020-6433-3

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics