This chapter reports the implementation details and experimental results of a SiP receiver analog-baseband (BB) IC for IEEE 802.11a/b/g WLAN. A new test strategy is introduced, which allows both functional-block and fullsystem measurements. Fabricated in a conventional 3.3-V 0.35-μm CMOS process without resorting to any specialized technology option, the verified techniques are directly migratable and are expected to yield higher performances in the forthcoming sub-1 V processes, of which the threshold voltages, forecasted by the International Technology Roadmap of Semiconductors (ITRS) [6.1], will be within 0.2–0.3 V in later technologies for hightier wireless applications.
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(2007). An Experimental 1-V Sip Receiver Analog-Baseband Ic For Ieee 802.11a/B/G Wlan. In: Analog-Baseband Architectures And Circuits For Multistandard And Lowvoltage Wireless Transceivers. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6433-3_6
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DOI: https://doi.org/10.1007/978-1-4020-6433-3_6
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