Variability in Nanoscale UTB SOI Devices and its Impact on Circuits and Systems

We have studied, using 3D statistical simulation, the variability in UTB SOI MOSFETs with sub 10nm dimensions introduced by random discrete dopants in the source/drain region, body thickness variation and line edge roughness. We have shown that the random dopants in the source/drain regions are the main source of variability in the studied devices. The results of the physical drift-diffusion simulation with quantum corrections are captured into statistical BSIMSOI compact model which are then used for statistical SRAM simulation. We have shown that SRAMs based on 10 nm UTB SOI transistor have less variability and better yield compared to SRAM based on 35 nm conventional (bulk) MOSFETs. However the scaling of the UTB SOI MOSFETs below 7.5 nm will cause significant yield and reliability problems in the corresponding UTB SOI SRAMs.