Charge trapping in self-aligned single-dot memory devices fabricated by UCL technology based on arsenic-assisted etching and oxidation effects is investigated. The devices demonstrate room-temperature single-electron trapping in the Si nanodot floating gate circa 16 nm in size. The pulse transfer (Id - Vg) characteristics and time evolution of the drain current (Id - t) technique are employed for determination of the total charge storage in the Si nanodot floating gate and the gate-nanodot capacitance of the devices.
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Nazarov, A.N., Lysenko, V.S., Tang, X., Reckinger, N., Bayot, V. (2007). Charge Trapping Phenomena in Single Electron NVM SOI Devices Fabricated by a Self-Aligned Quantum DOT Technology. In: Hall, S., Nazarov, A.N., Lysenko, V.S. (eds) Nanoscaled Semiconductor-on-Insulator Structures and Devices. NATO Science for Peace and Security Series B: Physics and Biophysics. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-6380-0_18
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DOI: https://doi.org/10.1007/978-1-4020-6380-0_18
Publisher Name: Springer, Dordrecht
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Online ISBN: 978-1-4020-6380-0
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