Capacitor Matching Insensitive High-Resolution Low-Power ADC Concept
A new implementation for cyclic and pipelined ADCs is presented in this chapter. A floatinghold- buffer is proposed which enables accurate addition of signal voltages without requiring precisely matching and linear components. A 1.5-bit algorithmic stage based on this floatinghold- buffer is presented and analysed in which voltage multiplication is replaced by voltage addition. The new technique is compared against existing techniques from the literature and the relative benefits are analysed.
KeywordsAlgorithmic Stage Pipeline ADCs Parasitic Capacitor Capacitor Mismatch Sampling Capacitor
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