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Multilevel Full-Chip Routing Considering Antenna Effect Avoidance

Part of the Analog Circuits And Signal Processing Series book series (ACSP)

As technology advances into nanometer territory, the antenna effect problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences reliability, manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high-density plasma. Furthermore, the continuous increase of the problem size in IC routing is also a great challenge to existing routing algorithms. In this chapter, we present a framework for multilevel full-chip routing with antenna avoidance using built-in jumper insertion approach.

Keywords

Gate Oxide Wire Length Benchmark Circuit Cumulative Length Perimeter Length 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer 2007

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