Multilevel Full-Chip Routing Considering Antenna Effect Avoidance
As technology advances into nanometer territory, the antenna effect problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences reliability, manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high-density plasma. Furthermore, the continuous increase of the problem size in IC routing is also a great challenge to existing routing algorithms. In this chapter, we present a framework for multilevel full-chip routing with antenna avoidance using built-in jumper insertion approach.
KeywordsGate Oxide Wire Length Benchmark Circuit Cumulative Length Perimeter Length
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