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Online Monitoring of Properties Built on Regular Expressions Sequences

  • Katell Morin-Allory
  • Dominique Borrione

We present an original method for generating monitors that capture sequence of events specified by logical and temporal properties under the form of assertions in declarative form written either in PSL or in SVA. The method includes an elementary monitor, a library of primitive connectors, a technique to interconnect them, and tokens either monochrome or polychrome. This results in a synthesizable digital module that can be properly connected to a digital system under verification. The complexity of the generation is proportional to the size of the sequence expression. Keywords PSL, hardware monitoring, VHDL, SVA, synthesis, debug

Keywords

Clock Cycle Regular Expression Operational Semantic Online Monitoring Syntax Tree 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer 2007

Authors and Affiliations

  • Katell Morin-Allory
    • 1
  • Dominique Borrione
    • 1
  1. 1.Tima LaboratoryFrance

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