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Multimode Δ-Σ-Based Fractional-N Frequency Synthesizer

Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

In chapter 4, we performed system-level simulation to aid the implementation of fractional-N synthesizers presented in this chapter. Effects of the different subblocks in the PLL on the entire phase noise of the closed-loop fractional-N synthesizer were monitored. In this chapter, unconditionally stable Δ-Σ modulators of the third order (namely MASH-1-1-1) are implemented and employed in a phase-locked loop fractional-N synthesizer providing a good average estimate for fractional-N dividers. Using a deep sub micron 0.18 µm CMOS process with a supply voltage of 1.8 V, a Δ-Σ-based fractional-N synthesizer is designed, simulated, laid out, fabricated, and tested. Results obtained from measurements on this synthesizer outperform all synthesizers reported to date [1, 2, 3, 4, 5, 6].

Keywords

Phase Noise Loop Filter Frequency Synthesizer Fractional Divider Noise Shaper 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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© Springer 2007

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