Several techniques have been proposed to reduce the energy consumption of ASIPs (Application-Specific Instruction set Processors). While those techniques can reduce the energy consumption with minimal change in the instruction set (IS), they often fail to exploit the opportunity of designing the entire IS from the energy-efficiency perspective. In this chapter we present an energy-efficient IS synthesis that can comprehensively reduce the energy-delay product (EDP) of ASIPs through optimal instruction encoding, considering both the instruction bitwidth and the dynamic instruction fetch count. Experimental results with a typical embedded RISC processor show that the proposed energy-efficient IS synthesis technique can generate application-specific ISs that are up to 40% more energy-efficient over the native IS for several application benchmarks.
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Lee, JE., Choi, K., Dutt, N.D. (2007). Synthesis of Instruction Sets for High-Performance and Energy-Efficient ASIP. In: Henkel, J., Parameswaran, S. (eds) Designing Embedded Processors. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-5869-1_3
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DOI: https://doi.org/10.1007/978-1-4020-5869-1_3
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