Power-Performance Modeling and Design for Heterogeneous Multiprocessors

  • JoAnn M. Paul
  • Brett H. Meyer

As single-chip systems are increasingly composed of heterogeneous multiprocessors an opportunity exists to explore new levels of low-power design. At the chip/system-level any processor is capable of executing any program (or task) with only differences in performance. When the system executes a variety of different task sets (loading), the problem becomes one of establishing the cost and benefit of matching task types to processor types under anticipated task loads on the system. This includes not only static task mapping, but dynamic scheduling decisions as well as the selection of the most appropriate set of processors for the system. In this chapter, we consider what models are appropriate to establish system-level power-performance trade-offs and propose some early design strategies in this new level of design.

Keywords

Europe Expense Mellon Cute 

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© Springer 2007

Authors and Affiliations

  • JoAnn M. Paul
  • Brett H. Meyer

There are no affiliations available

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