As single-chip systems are increasingly composed of heterogeneous multiprocessors an opportunity exists to explore new levels of low-power design. At the chip/system-level any processor is capable of executing any program (or task) with only differences in performance. When the system executes a variety of different task sets (loading), the problem becomes one of establishing the cost and benefit of matching task types to processor types under anticipated task loads on the system. This includes not only static task mapping, but dynamic scheduling decisions as well as the selection of the most appropriate set of processors for the system. In this chapter, we consider what models are appropriate to establish system-level power-performance trade-offs and propose some early design strategies in this new level of design.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J.M. Paul. Programmer’s Views of SoCs, International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), pp. 159-161, October 2003.
F. Karim, A. Mellan, A. Nguyen, U. Aydonat, T. Abdelrahman, A multi-level computing architecture for embedded multimedia applications, IEEE Micro, Vol. 24, pp. 56-66, 2004.
J.M. Paul, D.E. Thomas, A. Bobrek, Benchmark-based design strategies for single chip heterogeneous multiprocessors, International Confer-ence on Hardware/Software Codesign and System Synthesis (CODES-ISSS), pp. 54-59, 2004.
A.S. Cassidy, J.M. Paul, D.E. Thomas, Layered, multi-threaded, high-level performance design, 6th Design, Automation and Test in Europe (DATE), pp. 954-959, 2003.
J.M. Paul, A. Bobrek, J.E. Nelson, J.J. Pieper, D.E. Thomas, Schedulers as model-based design elements in programmable heterogeneous mul-tiprocessors, 40th Design Automation Conference (DAC), pp. 408-411, 2003.
A. Bobrek, J.J. Pieper, J.E. Nelson, J.M. Paul, D.E. Thomas, Mod-eling shared resource contention using a hybrid simulation/analytical approach, Design, Automation and Test in Europe (DATE), Vol. 2, pp. 1144-1149, 2004.
C.L. Seitz, System timing, Introduction to VLSI Systems, C. Mead, L. Conway, Eds., Reading, MA: Addison-Wesley, 1980.
T. Weiyu, R. Gupta, A. Nicolau, Power savings in embedded processors through decode filter cache, 5th Design Automation and Test in Europe (DATE), pp. 443-448, 2002.
B.H. Meyer, J.J. Pieper, J.M. Paul, J.E. Nelson, S.M. Pieper, A.G. Rowe, Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors, IEEE Transactions on Computers, vol. 54, Iss. 6, June 2005.
T.D. Burd, T.A. Pering, A.J. Stratakos, R.W. Brodersen, A dynamic voltage scaled micro-processor system, IEEE Journal of Solid-State Circuits, Vol. 35, pp. 1571-1580, 2000.
J.L. Henning, SPEC CPU2000: measuring CPU performance in the New Millennium, Computer, Vol. 33, Iss. 7, July 2000.
S. Woo, M. Ohara, E. Torrie, J. Sing, A. Gupta, The SPLASH-2 pro-grams: characterization and methodological considerations, International Symposium on Computer Architecture 1995, June 1995.
W.J. Dally, B. Towles, Route packets, not wires: on-chip interconnec-tion networks, Design Automation Conference 2001, 2001.
P. Babighian, L. Benini, E. Macii, Sizing and characterization of leakage-control cells for layout-aware distributed power-gating, Pro-ceedings of the Design, Automation and Test in Europe (DATE). 2004.
ARM7TDMI, http://www.arm.com/products/CPUs/ARM7TDMI.html, 2005.
ARM1136J(F)-S, http://www.arm.com/products/CPUs/ARM1136JFS.html, 2005.
TriCore 1 - 32-bit MCU-DSP Architecture, http://www.infineon. com/ cgi/ecrm.dll/ecrm/scripts/prod ov.jsp?oid=30926&cat oid= −83 62& stlnocount=true, 2005.
M. Mamidipaka, N. Dutt, eCacti: an enhanced power estimation model for on-chip caches, CECS Technical Report #04-28, University of California Irvine, 2004.
TriCore 32-bit Unified Processor DSP Kernel Benchmarks, http://www.infineon.com/cgi/ecrm.dll/ecrm/scripts/public_download.jsp?oid= 45812&parent_oid=30926, 2002.
Chipdir, http://www.xs4all.nl/∼ganswijk/chipdir/fam/arm/, 2005.
ARM7TDMI Product Overview, http://www.arm.com/pdfs/DVI0027B_7_R3.pdf, 2001
ARM7TDMI (Rev 4) Technical Reference Manual, http://www.arm.com/pdfs/DDI0210B_7TDMI_R4.pdf, 2003.
The ARM11Microarchitecture, http://www.arm.com/pdfs/ARM11MicroarchitectureWhite Paper.pdf, 2002.
ARM1026EJ-S r0p2TRM, http://www.arm.com/pdfs/DDI0211E_ arm1136_r0p2_trm.pdf, 2003.
T.L. Adam, K.M. Chandy, J.R. Dickson, A comparison of list schedules for parallel processing systems, Communications of the ACM, Vol. 17, pp. 685-690, Dec. 1974.
B.A. Shirazi, A.R. Hurson, K.M. Kavi, Scheduling and Load Balancing in Parallel and Distributed Systems, IEEE Computer Society Press, Los Alamitos, CA, 1995.
A. Jalabert, S. Murali, L. Benini, G.D. Micheli, xpipesCompiler: a tool for instantiating application specific networks on Chip, 7th Design, Automation and Test in Europe (DATE), 2004.
J.L. Hennessy, D.A. Patterson, Computer Architecture, Third Edition, Morgan Kaufmann, pp. 112, 138-9, 142, 2003.
T.T. Ye, L. Benini, G.D. Micheli, Analysis of power consumption on switch fabrics in network routers, 39th Design Automation Conference (DAC), 2002.
B.H. Meyer, Toward a new definition of optimality for programmable embedded systems, CMU-CSSI Tech Report No. CSSI 05-04.
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2007 Springer
About this chapter
Cite this chapter
Paul, J.M., Meyer, B.H. (2007). Power-Performance Modeling and Design for Heterogeneous Multiprocessors. In: Henkel, J., Parameswaran, S. (eds) Designing Embedded Processors. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-5869-1_19
Download citation
DOI: https://doi.org/10.1007/978-1-4020-5869-1_19
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-5868-4
Online ISBN: 978-1-4020-5869-1
eBook Packages: EngineeringEngineering (R0)