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Fault Tolerance in Programmable Circuits

  • Fernanda Lima Kastensmidt
  • Ricardo Reis

Abstract

This chapter is dedicated to the effects of radiation on programmable circuits. It is described the radiation effects on integrated circuits manufactured using CMOS process and it is explained in detail the difference between the effects of a SEU in an ASIC and in a SRAM-based FPGA architecture. It is also discussed some SEU mitigation techniques that can be applied at the FPGA architectural level. The problem of protecting SRAM-based FPGAs against radiation in the high level description is also defined.

Keywords

Combinational Logic SRAM Cell Single Event Transient Triple Modular Redundancy Single Event Upset 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer 2007

Authors and Affiliations

  • Fernanda Lima Kastensmidt
    • 1
  • Ricardo Reis
    • 1
  1. 1.Instituto de InformáticaUniversidade Federal do Rio Grande do SulPorto AlegreBrazil

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