RECONFIGURABLE A/D CONVERTERS FOR FLEXIBLE WIRELESS TRANSCEIVERS IN 4G RADIOS

  • Georges Gielen
  • Erwin Goris
  • Yi Ke

Abstract

Flexibility is a key feature in 4G telecom systems, where there is a demand for reconfigurable transceivers that can cope with multiple standards (cellular, WLAN, Bluetooth, etc.). Additionally, even within one mode, these transceivers should adapt to the environment (presence of received blockers or not, status of battery power levels, etc.) to minimize power consumption and optimize performance according to the needs of the customer and the desired Quality of Service. In addition, flexibility is required to cut the development time and cost to implement possible new future standards into the 4G system. All this calls for a digitally-controlled front-end architecture (“software-defined radio”) with reconfigurable RF and analog baseband blocks controlled through digital programmable software. This poses serious challenges to the design of such reconfigurable yet power-efficient RF/analog blocks. For the analog-to-digital converters in the receiver, this comes down to designing a power- and area-efficient reconfigurable converter with variable bandwidth and variable dynamic range. The general requirements for such converters in 4G systems will be described in this chapter. This will then be illustrated with the design of a reconfigurable continuous-time ∆∑ A/D converter with a pipelined multi-bit quantizer and 1-bit feedback. The prototype chip has been realized in a 0.18µm CMOS technology. It has 3 different modes (20 MHz BW/58dB SNDR, 4 MHz BW/60dB SNDR, 0.2MHz BW/70dB SNDR). The chip has an active area of 0.9mm2 and the power consumption for the most demanding mode (20 MHz/58 dB) is 37 mW.

Keywords

Kelly Erwin Teme 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    P. Kinget, M. Steyaert, Impact of transistor mismatch on the speed-accuracy-power tradeoff of analog CMOS circuits, proceedings Custom Integrated Circuits Conference (CICC), pp. 333–336, 1996.Google Scholar
  2. [2]
    A. Savla, Low-power design approaches for programmable-speed pipelined analog-to-digital converters, Master thesis Ohio State University, 2002.Google Scholar
  3. [3]
    L. Breems, A cascaded continuous-time ΔΣ modulator with 67dB dynamic range in 10MHz bandwidth, proc. IEEE International Solid-State Circuits Conference, pp. 72–73, 2004.Google Scholar
  4. [4]
    S. Patón, A. Di Giandomenico, L. Hernández, A.Wiesbauer, T. Pötscher, M. Clara, A 70-mW300-MHz CMOS continuous-time ΔΣ ADC with 15-MHz bandwidth and 11 bits of resolution, IEEE Journal of Solid-State Circuits, Vol. 39, pp. 1056–1063, July 2004.CrossRefGoogle Scholar
  5. [5]
    A. Tabatabaei, K. Onodera, M. Zargari, H. Samavati, D. Su, A dual channel ΔΣ ADC with 40MHz aggregate signal bandwidth, proc. IEEE International Solid-State Circuits Conference, pp. 66–67, 2003.Google Scholar
  6. [6]
    T. Burger, Q. Huang, A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSM dual-standard IF reception, IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1868–1878, December 2001.CrossRefGoogle Scholar
  7. [7]
    A. Dezzani and E. Andre, A 1.2-V dual-mode WCDMA/GPRS ΔΣ modulator, proc. IEEE International Solid-State Circuits Conference, pp. 58–59, 2003.Google Scholar
  8. [8]
    R. van Veldhoven, A tri-mode continuous-time ΔΣ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver, proc. IEEE International Solid-State Circuits Conference, pp. 60–61, 2003.Google Scholar
  9. [9]
    K. Gulati and H.-S. Lee, A low-power reconfigurable analog-to-digital converter, IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1900–1911, December 2001.CrossRefGoogle Scholar
  10. [10]
    Y. Geerts, High-performance CMOS Sigma-Delta converters, Ph.D. Dissertation Katholieke Universiteit Leuven, Belgium, May 2001.Google Scholar
  11. [11]
    T. Leslie and B. Singh, An improved Sigma-Delta modulator architecture, proc. IEEE International Symposium on Circuits and Systems, pp. 372–375, 1990.Google Scholar
  12. [12]
    T. Brooks, D. Robertson, D. Kelly, A. Del Muro, S. Harston, A cascaded Sigma-Delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR, IEEE Journal of Solid-State Circuits, Vol. 32, pp. 1896–1906, December 1997.CrossRefGoogle Scholar
  13. [13]
    P. Kiss, J. Silva, A. Wiesbauer, T. Sun, U-K Moon, J. Stonick, G. Temes, Adaptive digital correction of analog errors in MASHADCs - Part II. Correction using test-signal injection, IEEE Transactions on Circuits and Systems, part II, Vol. 47, pp. 629–638, July 2000.Google Scholar

Copyright information

© Springer 2006

Authors and Affiliations

  • Georges Gielen
  • Erwin Goris
  • Yi Ke

There are no affiliations available

Personalised recommendations