• Georges Gielen
  • Erwin Goris
  • Yi Ke


Flexibility is a key feature in 4G telecom systems, where there is a demand for reconfigurable transceivers that can cope with multiple standards (cellular, WLAN, Bluetooth, etc.). Additionally, even within one mode, these transceivers should adapt to the environment (presence of received blockers or not, status of battery power levels, etc.) to minimize power consumption and optimize performance according to the needs of the customer and the desired Quality of Service. In addition, flexibility is required to cut the development time and cost to implement possible new future standards into the 4G system. All this calls for a digitally-controlled front-end architecture (“software-defined radio”) with reconfigurable RF and analog baseband blocks controlled through digital programmable software. This poses serious challenges to the design of such reconfigurable yet power-efficient RF/analog blocks. For the analog-to-digital converters in the receiver, this comes down to designing a power- and area-efficient reconfigurable converter with variable bandwidth and variable dynamic range. The general requirements for such converters in 4G systems will be described in this chapter. This will then be illustrated with the design of a reconfigurable continuous-time ∆∑ A/D converter with a pipelined multi-bit quantizer and 1-bit feedback. The prototype chip has been realized in a 0.18µm CMOS technology. It has 3 different modes (20 MHz BW/58dB SNDR, 4 MHz BW/60dB SNDR, 0.2MHz BW/70dB SNDR). The chip has an active area of 0.9mm2 and the power consumption for the most demanding mode (20 MHz/58 dB) is 37 mW.


Power Consumption Quantization Noise Noise Transfer Function Prototype Chip Radio Design 
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© Springer 2006

Authors and Affiliations

  • Georges Gielen
  • Erwin Goris
  • Yi Ke

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