Calibration-Free High-Resolution Low-Power Algorithmic and Pipelined AD Conversion
A novel implementation for algorithmic and pipelined ADCs is presented in this paper. A floating voltage hold buffer is proposed which enables the accurate addition of signal voltages without requiring precisely matching and linear components. A new 1.5-bit stage is presented based on the floating hold buffer in which voltage multiplication is replaced by voltage addition. An experimental 12-bit 3.3 MS/s algorithmic ADC in 0.25μm standard CMOS for a 2V application is described. It occupies O.15mm2 of die area and dissipates 5.5mW. The power and area FOMs are well below those previously reported for 1.5-bit algorithmic ADC stages.
KeywordsParasitic Capacitor Capacitor Mismatch Sampling Capacitor Voltage Addition Hold Mode
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