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Calibration-Free High-Resolution Low-Power Algorithmic and Pipelined AD Conversion

  • Patrick J. Quinn
  • Maxim P. Pribytko
  • Arthur H. M. van Roermund

Abstract

A novel implementation for algorithmic and pipelined ADCs is presented in this paper. A floating voltage hold buffer is proposed which enables the accurate addition of signal voltages without requiring precisely matching and linear components. A new 1.5-bit stage is presented based on the floating hold buffer in which voltage multiplication is replaced by voltage addition. An experimental 12-bit 3.3 MS/s algorithmic ADC in 0.25μm standard CMOS for a 2V application is described. It occupies O.15mm2 of die area and dissipates 5.5mW. The power and area FOMs are well below those previously reported for 1.5-bit algorithmic ADC stages.

Keywords

Parasitic Capacitor Capacitor Mismatch Sampling Capacitor Voltage Addition Hold Mode 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 2004

Authors and Affiliations

  • Patrick J. Quinn
    • 1
  • Maxim P. Pribytko
    • 1
  • Arthur H. M. van Roermund
    • 2
  1. 1.Xilinx, IC designCitywest Business Campus, Logic DriveSaggart, DublinIreland
  2. 2.Department of Electrical EngineeringEindhoven University of TechnologyEindhovenThe Netherlands

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