Calibration-Free High-Resolution Low-Power Algorithmic and Pipelined AD Conversion

  • Patrick J. Quinn
  • Maxim P. Pribytko
  • Arthur H. M. van Roermund

Abstract

A novel implementation for algorithmic and pipelined ADCs is presented in this paper. A floating voltage hold buffer is proposed which enables the accurate addition of signal voltages without requiring precisely matching and linear components. A new 1.5-bit stage is presented based on the floating hold buffer in which voltage multiplication is replaced by voltage addition. An experimental 12-bit 3.3 MS/s algorithmic ADC in 0.25μm standard CMOS for a 2V application is described. It occupies O.15mm2 of die area and dissipates 5.5mW. The power and area FOMs are well below those previously reported for 1.5-bit algorithmic ADC stages.

Keywords

Dust Propa Resi Settling Paral 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    H. Schmid, Electronic Analog/Digital Conversions, Van Nostrand-Reinhold, p.195, 1970.Google Scholar
  2. [2]
    Robert H. McCharles, Vikram A. Saletore, William C. Black, David A. Hodges “An Algorithmic Analog-to-Digital Converter”, IEEE ISSCC, SECTION IX, pp. 96–97, 1977.Google Scholar
  3. [3]
    Y. Ren, B. H. Leung, Y-M. Lin, “A Mismatch-Independent DNL Pipelined Analog-to-Digital Converter,” IEEE Trans. Circuits and Systems II: Proc. Analog and Digital Processing, vol. 46, no. 5, pp. 517–526, May, 1999.Google Scholar
  4. [4]
    Thomas B. Cho and Paul R. Gray, “A 10 b, 20 Msample/s, 35mW Pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166–172, Mar, 1995.CrossRefGoogle Scholar
  5. [5]
    David W. Cline and Paul R. Gray, “A Power Optimized 13-b 5 Msamples/s Pipelined Analog-to-Digital Converter in 1.2 μn CMOS,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 294–303, Mar, 1996.CrossRefGoogle Scholar
  6. [6]
    Bang-Sup Song, Michael F. Tompsett, Kadaba R. Lakshmikumar “A 12-bit 1-Msample/s Capacitor Error-Averaging Pipelined A/D Converter. ” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1324–1332, Dec, 1988.CrossRefGoogle Scholar
  7. [7]
    Lauri Sumenen, Mikko Waltari, Kari A. I. Halonen “A 10-b 200-MS/s CMOS Parallel Pipeline A/D Converter” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1048–1055, July 2001.CrossRefGoogle Scholar
  8. [8]
    Hae-Seung Lee, “A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC,” IEEE J. Solid State Circuits, vol. 29, no. 4, pp. 509–515, Apr. 1994.CrossRefGoogle Scholar
  9. [9]
    Shang-Yuan Chuang, Terry L. Sculley “A Digitally Self-Calibrating 14-bit 10-MHz CMOS Pipelined A/D Converter” IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 674–683, June 2002.CrossRefGoogle Scholar
  10. [10]
    Krishnaswami Nagaraj “Efficient Circuit Configurations for Algorithmic Analog to Digital Converters”, IEEE Trans. Circuits and Systems II: Proc. Analog and Digital Processing, Vol.40, No.12, pp.777–785, Dec. 1993.Google Scholar
  11. [11]
    Stephen H. Lewis and Paul Gray, “A Pipelined 5-Msample/s 9-bit Analog-toDigital Converter.” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 954–961, Dec. 1987.CrossRefGoogle Scholar
  12. [12]
    W. Yang, D. Kelly, I. Mehr, M. Sayuk, L. Singer, “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input”, IEEE J. Solid State Circuits, vol. 36, no. 12, pp. 1931–1936, Dec, 2001.CrossRefGoogle Scholar
  13. [13]
    Stephen H. Lewis, “Optimizing the Stage Resolution in Pipelined, Multstage, Analog-to-Digital Converters for Video Rate Applications,” IEEE Trans. Circuits and Systems II: Proc. Analog and Digital Processing, vol. 39, no. 8, pp. 516–523, Aug, 1992.Google Scholar
  14. [14]
    Andrew M. Abo and Paul R. Gray, “A 1.5-V, 10-bit, 14.3 MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE J. Solid State Circuits, vol. 34, no. 5, pp. 599–606, May, 1999.CrossRefGoogle Scholar
  15. [15]
    P. J. Quinn, K. van Hartingsveldt, A.H.M. van Roermund, “A 10.7-MHz CMOS SC Radio IF Filter Using Orthogonal Hardware Modulation,” IEEE J. SolidState Circuits, vol. 35, no. 12, pp. 1865–1876, Dec, 2000.CrossRefGoogle Scholar
  16. [16]
    Douglas Brooks, “Differential Signals, The Differential Difference !”, Printed Circuit Design, CMP Publication, May 2001.Google Scholar
  17. [17]
    Klaas Bult and Govert J. G. M. Geelen “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain”IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1379–1384, Dec. 1990.CrossRefGoogle Scholar
  18. [18]
    O. Erdogan, P. J. Hurst, S. H. Lewis, “A 12-b Digital-Background-Calibrated Algorithmic ADC with -90-dB THD”, IEEE J. Solid State Circuits, vol. 34, no. 12, pp. 1812–1820, Dec, 2001.CrossRefGoogle Scholar
  19. [19]
    Shafiq M. Jamal, Diahong Fu, Nick C.-J. Chang, Paul J. Hurst, Stephen H. Lewis “A 10-b 120-Msample/s Time-Interleaved Analog-to-Digital Converter With Digital Background Calibration.” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1618–1627, Dec. 2002.CrossRefGoogle Scholar
  20. [20]
    Iuri Mehr and Larry Singer “A 55-mW, 10-bit, 40-MSamples/s Nyquist-Rate CMOS DC” AIEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 318–324, March 2000.CrossRefGoogle Scholar
  21. [21]
    Myung-Jun Choe, Bang-Sup Song, Kantilal Barcania “An 8-b 100-MSample/s CMOS Pipelined Folding ADC” IEEE J. Solid-State Circuits, vol. 36, no. 2, pp. 184–194, Feb. 2001.CrossRefGoogle Scholar
  22. [22]
    Jun Ming, Stephen Lewis “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration” IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1489–1497, Oct. 2001.CrossRefGoogle Scholar
  23. [23]
    Hendrik van der Ploeg, Gian Hoogzaad, Henk A. H. Termeer, Maarten Vertregt“A 2.5-V 12-b 54-Msample/s 0.25-um CMOS ADC in 1-mm2 With Mixed-Signal Chopping and Calibration” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1859–1867, Dec. 2001.CrossRefGoogle Scholar
  24. [24]
    Ming-Huang Liu and Shen Iuan Liu “An 8-bit 10MS/s Folding and Interpolating ADC Using the Continuous-Time Auto-Zero Technique” IEEE J. SolidState Circuits, vol. 36, no. 1, pp. 122–128, Jan 2001.CrossRefGoogle Scholar
  25. [25]
    Myung-Jun Choe, Bang-Sup Song, Kantilal Barcania “A 13-b 40-MSamples/s CMOS Pipelined Folding ADC with Background Offset Trimming” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1781–1790, Dec. 2000.CrossRefGoogle Scholar
  26. [26]
    Ion E. Opris, Bill C. Wong and Sing W. Chin “A Pipeline A/D Converter Architecture with Low DNL” IEEE J. Solid-State Circuits, vol. 36, no. 2, pp. 281–285, Feb. 2000.CrossRefGoogle Scholar
  27. [27]
    Siamak Mortezapour and Edward Lee, “A 1-V, 8-bit Successive Approximation ADC in Standard CMOS Process,” IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 642–646, Apr 2000.CrossRefGoogle Scholar
  28. [28]
    Michael Scott, Bernhard Boser and Kristofer Pister, “An Ultralow-Energy ADC for Smart Dust,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1123–1129, July 2003.CrossRefGoogle Scholar
  29. [29]
    Boris Murmann and Bernhard Boser, “A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040–2049, Dec 2003.CrossRefGoogle Scholar
  30. [30]
    Patrick Quinn and Maxim Pribytko, “Capacitor Matching Insensitive 12-bit 3.3 MS/s Algorithmic ADC in 0.25µm CMOS,” in IEEE 2003 Proc. Custom Integrated Circuits Conf., San Jose, Sept. 2003, pp. 425–428.Google Scholar
  31. [31]
    Maxim Pribytko and Patrick Quinn, “A CMOS Single-Ended OTA With High CMRR,” in Proc. 29th Eur. Solid-State Circuits Conf., Estoril, Portugal, Sept. 2003, pp. 293–296.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2004

Authors and Affiliations

  • Patrick J. Quinn
    • 1
  • Maxim P. Pribytko
    • 1
  • Arthur H. M. van Roermund
    • 2
  1. 1.Xilinx, IC designCitywest Business Campus, Logic DriveSaggart, DublinIreland
  2. 2.Department of Electrical EngineeringEindhoven University of TechnologyEindhovenThe Netherlands

Personalised recommendations