In chapter 1, layout synthesis was defined as ‘the generation of the physical layout of a design from a corresponding abstract structural description’. In recent years, considerable interest has been generated in the development of suitable tools for the layout of logic networks for ASIC implementation. The facilities provided by these tools are usually dependent on the chosen implementation technology and design style. Automatic layout systems are commonly used for both gate array and standard cell design styles (Soukup, 1981).
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