Abstract
A computer consists of many logic circuits. These may be connected in many ways, but in principle their organisation is as shown in figure 4.1.
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Further Reading
G. Cheroff, D. L. Critchlow, R. H. Dennard and L. M. Terman. IGFET circuit performance —n-channel versus p-channel. IEEE J. Solid State Circuits, SC-4 (1969) 267
T. Masuhara, M. Nagata and N. Hashimoto. A high-performance n-channel MOS LSI using depletion-type load elements. IEEE J. Solid-State Circuits, SC-7 (1972) 224
R. H. Crawford and B. Bazin. Theory and design of MOS capacitor pull-up circuits. IEEE J. Solid State Circuits, SC-4 (1969) 145
B. Watkins. A low-power multiphase circuit technique. IEEE J. Solid State Circuits, SC-2 (1967) 213
Y. T. Yen. Transient analysis of four-phase MOS switching circuits. IEEE J. Solid State Circuits, SC-3 (1968) 1
J. F. Allison, F. P. Heiman and J. R. Burns. Silicon-on-sapphire complementary MOS memory cells. IEEE J. Solid State Circuits, SC-2 (1967) 208
J. R. Burns. Large-signal transit-time effects in the MOS-transistor. RCA Rev., 30 (1969) 15
Y. T. Yen. Intermittent failure problems of four-phase MOS circuits. IEEE J. Solid State Circuits, SC-4 (1969) 107
T. Klein. Technology and performance of integrated complementary MOS circuits. IEEE J. Solid State Circuits, SC-4 (1969) 122
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© 1974 J. T. Wallmark and L. G. Carlstedt
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Wallmark, J.T., Carlstedt, L.G. (1974). MOS Transistors in Digital Circuits. In: Field-Effect Transistors in Integrated Circuits. Palgrave, London. https://doi.org/10.1007/978-1-349-02053-9_5
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DOI: https://doi.org/10.1007/978-1-349-02053-9_5
Publisher Name: Palgrave, London
Print ISBN: 978-1-349-02055-3
Online ISBN: 978-1-349-02053-9
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