Abstract
Processors with concurrent error detection (CED) capability are called self-checking processors. CED is a very important and necessary feature in VLSI microprocessors that are integral and ultradependable for real-time applications. The design of self-checking reduced instruction set computer (RISC) requires the state-of-the-art techniques in computer architectures, implementation and self-checking designs.
Among the components of a processor, the most difficult circuits to check are the arithmetic and logic units (ALUs). In this chapter, we shall concentrate on the design of a self-checking ALU. We introduce a new totally self-checking (TSC) ALU design scheme called Berger check prediction (BCP). Using the BCP, the self-checking processor design can be made very efficient. Also, we discuss the theory involving the use of a reduced Berger code for a more efficient BCP design. A novel design for a Berger code checker based on a generalized code partitioning scheme is discussed here, and is used to efficiently implement the Berger code checking.
This work was supported by the Office of Naval Research under Grant N00014-91-J-1067.
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© 1994 Kluwer Academic Publishers
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Rao, T.R.N., Feng, GL., Kolluru, M.S. (1994). Design of Self-Checking Processors Using Efficient Berger Check Prediction Logic. In: Koob, G.M., Lau, C.G. (eds) Foundations of Dependable Computing. The Kluwer International Series in Engineering and Computer Science, vol 285. Springer, Boston, MA. https://doi.org/10.1007/978-0-585-28002-8_2
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DOI: https://doi.org/10.1007/978-0-585-28002-8_2
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