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Low-Power Circuit Design

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Sensors and Low Power Signal Processing

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Abstract

Low-voltage (LV), low-power (LP) circuit design requires special attention on device behavior, and the best circuit topology needs to be chosen to meet the design challenges. With the scaling of MOS devices, supply voltage is reduced with each technological leap, but the threshold voltage and the drain-to-source saturation voltage are not scaling at the same rate because of the subthreshold current consideration in mixed-signal environment. Therefore, conventional circuit design topologies are not best suited for deep submicron (DSM) CMOS design. This chapter is a brief overview of the scaling concept of MOS devices and low-power circuit design topologies using deep submicron CMOS process.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Tennessee, Knoxville, TN, USA

    Syed Kamrul Islam

  2. Department of Engineering Science, Sonoma State University, Rohnert Park, CA, USA

    Mohammad Rafiqul Haider

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  1. Syed Kamrul Islam
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  2. Mohammad Rafiqul Haider
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Correspondence to Syed Kamrul Islam .

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Islam, S.K., Haider, M.R. (2010). Low-Power Circuit Design. In: Sensors and Low Power Signal Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-79392-4_3

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  • DOI: https://doi.org/10.1007/978-0-387-79392-4_3

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  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-79391-7

  • Online ISBN: 978-0-387-79392-4

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