Advanced Chip-to-Substrate Connections

Abstract

Transistor scaling, shrinking the critical dimensions of the transistor, has led to continuous improvements in system performance and cost. Higher density of the transistors and larger chip size has also led to new challenges for chip-to-substrate connections. The pace of change in packaging and chip-to-substrate connections has accelerated because off-chip issues are increasingly a limiting factor in product cost and performance. Chip-to-substrate connections are challenged on many fronts, including number of signal input-output (I/O) connections, I/O that operate at high-speed, power & ground I/O, and low cost.

This chapter examines various techniques and structures that have been designed to address these challenges. The mechanical compliance and electrical performance modeling of the interconnect structures is important in determining the geometry, materials, and processing necessary for an application. Various approaches have been taken to satisfy both the mechanical and electrical needs for these I/O connections. Mechanically compliant structures based on traditional solder bonded connections can drastically improve thermo-mechanical reliability but may compromise electrical performance. Additional structures improve upon the compliance of the solder ball by capping a pillar structure with solder, but still require the reliable protection of underfill. More high performance and long term improvements to satisfy both mechanical and electrical needs such as interconnects composed entirely of copper are also discussed. Finally, the future needs projected by the ITRS for ultra-high off-chip frequency and thermal management are addressed with respect to chip-to-substrate interconnects.