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Acknowledgments
The authors wish to thank for their contributions (1) the following IBM personnel: Steven Steen, Kuan-neng Chen, Leathen Shi, Cornelia Tsang, Paul Andry, David Frank, Jyotica Patel, James Vichiconti, Deborah Neumayer, Narender Rana, Robert Trzcinski, Latha Ramakrishnan, Roy Yu, James Tornello, Michael Lofaro, Gill Singco, John Ott, David DiMilia, William Price, Jesus Acevedo, and (2) the following RPI personnel: Dr. James Lu, Dr. Sang Hwui Lee, Dr. Ravi Kumaroh. The authors also acknowledge the support of IBM’s MRL and CSS as well as staff at EV Group and Suss MicroTec.
This project was partially funded by DARPA under contract numbers N66001-00-C-8003 and N66001-04-C-8032.
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Topol, A.W., Koester, S.J., La Tulipe, D.C., Young, A.M. (2008). 3D Fabrication Options for High-Performance CMOS Technology. In: Tan, C., Gutmann, R., Reif, L. (eds) Wafer Level 3-D ICs Process Technology. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-76534-1_9
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