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References
Jones RE, Chatterjee R, Pozder S (2007) Technology and application of 3D interconnect. In: Proc IEEE Intern Conf Integrated Circuit Design and Techn, pp 176–179
Banerjee K, Souri S, Kapur P, Saraswat K (2001) 3-D ICs: A novel chip design for improving deep-submicron interconnect performance and system-on-chip integration. Proc IEEE 89:602–633
Meindl JD, Davis JA, Zarkesh-Ha P, Patel CS, Martin KP, Kohl PA (2002) Interconnect opportunities for gigascale integration. IBM J Res Dev 46:245–263
Zeng A, Lii J, Rose K, Gutmann RJ (2005) First-order performance prediction of cache memory with wafer-level 3D integration. IEEE Design Test Comput 22:548–555
Kunio K, Oyama K, Hayashi Y, Morimoto M (1989) Three dimensional ICs, having four stacked active device layers. In: IEDM Technical Digest, pp 837–840
Jung SM, Jang J, Cho W, Moon J, Kwak K, Choi B., Hwang, B, Lim H, Jeong, J, Kim J, Kim K (2004) The revolutionary and truly 3-dimensional 25F2 SRAM technology with the smallest S3 (stacked single-crystal Si) cell, 0.16 μm2, and SSTFT (stacked single-crystal thin film transistor) for ultra high density SRAM. In: VLSI Technology Digest Technical Papers, pp 228–229
Xue L, Liu CC, Tiwari S (2001) Multi-layers with buried structures (MLBS): an approach to three-dimensional integration. In: Proc IEEE Intern SOI Conf, pp 117–118
Sailer PM, Singhal P, Hopwood J, Kaeli DR, Zavracky PM, Warner K, Vu DP (1997) Creating 3D circuits using transferred films. IEEE Circuits Devic Mag 13:27–30
Topol A, La Tulipe DC, Shi L, Alam SM, Frank DJ, Steen SE, Vichiconti J, Posillico D, Cobb M, Medd S, Patel J, Goma S, DiMilla D, Robson MT, Duch E, Farinelli M, Wang C, Conti RA, Canaperi DM, Deligianni L, Kumar A, Kwietniak KT, D’Emic C, Ott J, Young AM, Guarini KW, Ieong M (2005) Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs). In: IEDM Technical Digest, pp 352–355
Chen KN, Fan A, Tan CS, Reif R, Wen CY (2002) Abnormal contact resistance reduction of bonded copper interconnects in three-dimensional integration during current stressing. Appl Phys Lett 81:3774–3776
Morrow P, Kobrinsky MJ, Ramanathan S, Chang-Min P, Harmes M, Ramachandrarao V, Hyun-mog P, Kloster G, List S, Kim S (2004) Wafer-level 3D interconnects via Cu bonding. In: Proc Adv Metallization Conf, pp 125–130
Ramm P, Klumpp A, Merkel R, Weber J, Wieland R, Ostmann A, Wolf J (2003) 3D system integration technologies. In: McKerrow AJ, Leu J, Kraft O, Kikkawa T (eds) Mater Res Soc Symp Proc, vol 766, pp 3–14
McMahon JJ, Lu J-Q, Gutmann RJ (2005) Wafer bonding of damascene-patterned metal/adhesive redistribution layers for via-first three-dimensional (3D) interconnect. In: Proc 55th Electronic Components and Technology Conf, vol 1, pp 331–336
Kostner H, Huebner H (2003) New flip-chip on chip process supercedes embedded technologies. In: Proc 14th European Microelectronics and Packaging Conf & Exposition
Pozder S, Chatterjee R, Jain A, Huang Z, Jones RE, Acosta E (2007) Progress of 3D integration technologies and 3D interconnects. In: Proc IEEE International Interconnect Techn Conf, pp 213–215
Steen SE, LaTulipe D, Topol AW, Frank DJ, Belote K, Posillico D (2007) Overlay as the key to drive wafer scale 3D integration. Microelectron Eng 84:1412–1415
Okada Y, Tokumaru Y (1984) Precise determination of lattice parameter and thermal expansion coefficient of silicon between 300 and 1500 K. J Appl Phys 56:314–320
Kemevez N (2006) Innovations in 3-D circuit via direct bonding technologies. In: Proc RTI sponsored 3D Architectures for Semiconductor Integration and Packaging, conf session 7
Scheiring C, Kostner H, Lindner P, Pargfrieder S (2005) 3-D integration of ICs. Adv Packag 14:26–28
van Zeijl HW, Slabbekoorn J, Nanver LK, van Dijk PWL, Berthold A, Machielsen T (2000) Backwafer optical lithography and wafer distortion in substrate transfer technologies. In: Proc Intern Society of Optical Engineering (SPIE), vol 4181, pp 200–207
Guarini KW, Topol AW, Ieong M, Yu R, Shi L, Newport MR, Frank DJ, Singh DV, Cohen GM, Nitta SV, Boyd DC, O’Neil PA, Tempest SL, Pogge HB, Purushothaman S, Haensch WE (2002) Electrical integrity of state-of-the-art 0.13 μm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit(IC) fabrication. In: IEDM Technical Digest, pp 943–945
Pozder S, Jones R, Adams V, Li H-F, Canonico M, Zollner S, Lee SH, Gutmann RJ, Lu J-Q (2006) Exploration of the scaling limits of 3D integration. In: Bower CA, Garrou PE, Ramm P, Takahashi K (eds) Mater Res Soc Symp Proc, vol. 970, 0970-Y02-01
Ezaki T, Kondo K, Ozaki H, Sasaki N, Yonemure H, Kitano M, Tanaka S, Hirayama, T (2004) A 160 Gb/s interface design configuration for multichip LSI. In: Proc Intern Solid-State Circuits Conf, pp 140–141
Alam SM, Jones RE, Rauf S, Chatterjee R (2007) Inter-strata characteristics and signal transmission in three-dimensional (3D) integration technology. In: Proc IEEE Intern Symp Quality Electronics Design, pp 580–585
Black B, Nelson DW, Webb C, Samra N (2004) 3D processing technology and its impact on iA32 microprocessors. In: Proc IEEE Intern Conf on Computer Design, 1063-6404/04, pp 316–318
Bautista J (2007) Tera-scale computing – the role of interconnects in volume compute platforms. In: IEEE Intern Interconnect Techn Conf, pp 187–189
Lee K (2006) The next generation package technology for higher performance and smaller systems. In: Presentations CD: 3D Architectures for Semiconductor Integration and Packaging
Kurino H, Lee KW, Nakumura T, Sakuma K, Park KT, Miyakawa N, Shimazutsu H, Kim KY, Inamura K, Koyanagi M (1999) Intelligent image sensor chip with three dimensional structure. In: IEDM Technical Digest, pp 879–882
Kurino H, Nakagawa Y, Nakamura T, Yamada Y, Lee K-W, Koyanagi M (2001) Biologically inspired vision chip with three dimensional structure. IEICE Trans Electron Jpn E84-C:1717–1722
Aull B, Burns J, Chenson C, Felton B, Hanson H, Keast C, Knecht J, Loomis A, Renzo M, Soares A, Suntharalingam V, Warner K, Wolfson D, Yost D, Young D (2006) Laser radar imager based on 3D integration of Geiger-mode avalanche photodiodes with two SOI timing circuit layers. In: IEEE Intern Solid-State Circuits Conf Digest of Techn Papers, paper 16.9
Temple D, Bower A, Malta D, Robinson JE, Coffman PR, Slokan MR, Welch TB (2006) High density 3-D integration technology for massively parallel signal processing in advanced infrared focal plane array sensors. IEDM Technical Digest, 10.1109/IEDM.2006.346980
Motoyoshi M, Kamibayashi K, Koyanagi M, Bonkohara M (2007) Current and future 3 dimensional LDI technologies. In: Proc 3D- System Integration Conf (Japan)
Beyne E (2006) 3D system integration technologies. In: Intern Symp VLSI Techn Systems Applications, pp 19–27
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Pozder, S.K., Jones, R.E. (2008). Status and Outlook. In: Tan, C., Gutmann, R., Reif, L. (eds) Wafer Level 3-D ICs Process Technology. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-76534-1_15
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