# Variability-Aware Frequency Scaling in Multi-Clock Processors

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## Introduction

Variability is becoming a key concern for microarchitects as technology scaling continues and more and more increasingly ill-defined transistors are placed on each die. Process variations during fabrication result in a nonuniformity of transistor delays across a single die, which is then compounded by dynamic thermally dependent delay variation at runtime.

The delay of every critical path in a synchronously timed block must be less than the proposed cycle time for the block as a whole to meet that timing constraint. Thus, as both the amount of variation (due to ever-shrinking feature sizes as well as greater temperature gradients) and the number of critical paths (due to increasing design complexity and levels of integration) grow, the reduction in clock speed necessary to reduce the probability of a timing violation to an acceptably small level increases. However, the worst-case delay is very rarely exercised, and as a result, the overdesign that is necessary to deal with...

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