Architectural Techniques for Adaptive Computing

  • Shidhartha Das
  • David Roberts
  • David Blaauw
  • David Bull
  • Trevor Mudge
Part of the Series on Integrated Circuits and Systems book series (ICIR)


As critical geometries shrink to the 45 nm region and beyond, lithographic limitations have led to rising intra- and inter-die process variations. Increased variability makes it significantly difficult to accurately model transistor behavior on silicon, and often probabilistic methods are required [1]. The consequent loss in silicon predictability implies that design uncertainties become severe and are made even worse at the lower supply voltages used for future technologies [2].

In addition to process variability, deep sub-micron technologies also suffer from increased power consumption which compromises structural reliability of processors. Indeed, as current densities have increased, chip failure through effects like electro-migration [3] and time-dependent dielectric breakdown (TDDB) [4] has become major challenge, especially for high-end processors. Furthermore, at lower supply voltages, noise margins for sensitive circuits significantly reduce. Consequently, signal...


Supply Voltage Error Detection Critical Path Timing Error Dynamic Voltage Scaling 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Shidhartha Das
    • 1
    • 2
  • David Roberts
    • 2
  • David Blaauw
    • 2
  • David Bull
    • 1
  • Trevor Mudge
    • 2
  1. 1.ARM LtdUK
  2. 2.University of Michigan

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