Sensors for Critical Path Monitoring

  • Alan Drake
Part of the Series on Integrated Circuits and Systems book series (ICIR)

Variability and Its Impact on Timing

Modern processes are becoming more sensitive to noise [25]. In addition to technology parameters having larger variation with each new technology generation [1], [20], timing sensitivity to such environmental conditions as temperature [19], [31], aging [3], workload [19], [13], cross-talk noise in wires [18], NBTI [12], and many other effects is increasing.

Noise processes that effect timing are described as random or systematic, and they are measured from die to die and within die [6], [32]. Random noise is less dependent on the integrated circuit’s design than systematic noise and it is characterized by a number of statistics such as its mean and standard deviation. Systematic noise results from characteristics of the manufacturing process or from the physical design and can be predicted once the underlying process causing the variation is understood. For example, the wire thickness in technologies that use copper metallization is dependent on...


  1. [1]
    K. Agarwal and S. Nassif, “Characterizing Process Variation in Nanometer CMOS,” DAC, 4–8 June 2007, pp. 396–399.Google Scholar
  2. [2]
    T. Austin, D. Blaauw, T. Mudge, and K. Flautner, “Making Typical Silicon Matter with Razor,” Computer, vol. 27, no. 3, Mar 2004, pp. 57–65.CrossRefGoogle Scholar
  3. [3]
    J. Blome, S. Feng, S. Gupta, and S. Mahlke, “Self-Calibrating Online Wearout Detection,” MICRO, 1–5 Dec 2007.Google Scholar
  4. [4]
    S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, “Parameter Variations and Impact on Circuits and Microarchitecture,” DAC, 2–6 June 2003, pp. 338–342.Google Scholar
  5. [5]
    K. Bowman, S. Duvall, and J. Meindl, “Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration,” IEEE J. Solid-State Circuits, vol. 37, no. 2, Feb 2002, pp. 183–190.CrossRefGoogle Scholar
  6. [6]
    K. Bowman, S. Samaan, and N. Hakim, “Maximum Clock Frequency Distribution Model with Practical VLSI Design Considerations,” Integrated Circuit Design and Technology, 17–20 May 2004, pp. 183–191.Google Scholar
  7. [7]
    Cool ‘n’ Quiet Technology Installation Guide for AMD Athlon 64 Processor Based Systems. AMD, Corp. CA [Online] 0.04, 2004, June. Quiet_Installation_Guide3.pdf.
  8. [8]
    A. Drake, (2005), Power Reduction in Digital Systems Through Local Resonant Clocking and Dynamic Threshold MOS, Ph.D. Dissertation, University of Michigan.Google Scholar
  9. [9]
    A. Drake, R. Senger, H. Deogun, G. Carpenter, S. Ghiasi, T. Nguyen, N. James, M. Floyd, and V. Pokala, “A Distributed Critical-Path Monitor for a 65 nm High-Performance Microprocessor,” ISSCC, 11–15 Feb 2007, pp. 398–399.Google Scholar
  10. [10]
    M. Elgebaly and M. Sachdev, “Variation-Aware Adaptive Voltage Scaling System,” IEEE Transactions on VLSI Systems, vol. 15, no. 5, May 2007, pp. 560—571.CrossRefGoogle Scholar
  11. [11]
    Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor, Order No. 301170-001. Intel, Corp. OR. [Online]. 2004, March. technology/silicon/power/chipdesign.htm.
  12. [12]
    M. Ershov, S. Saxena, H. Karbasi, S. Winters, S. Minehane, J. Babcock, R. Lindley, P. Clifton, M. Redford, and A. Shibkov, “Dynamic Recovery of Negative Bias Temperature Instability in p-type Metal-Oxide-Semiconductor Field-Effect Transistors,” Applied Physics Letters, vol. 83, no. 8, 25 Aug 2003, pp. 1647–1649.CrossRefGoogle Scholar
  13. [13]
    E. Fetzer, “Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design,” IEEE Design and Test of Computers, vol. 23, no. 6, Nov/Dec 2006, pp. 476–483.CrossRefGoogle Scholar
  14. [14]
    T. Fischer, J. Desai, B. Doyle, et al., “A 90-nm Variable Frequency Clock System for Power-Managed Itanium Architecture Processor,” IEEE J. Solid-State Circuits, vol. 41, no. 1, Jan 2006, pp. 218–228.CrossRefGoogle Scholar
  15. [15]
    B. Garlepp, K. Donnelly, J. Kim, P. Chau, J. Zerbe, C. Huang, C. Tran, C. Portmann, D. Stark, Y.-F. Chan, T. Lee, and M. Horowitz, “A Portable Digital DLL for High-Speed CMOS Interface Circuits,” IEEE J. Solid-State Circuits, vol. 34, no. 5, May 1999, pp. 632–644.CrossRefGoogle Scholar
  16. [16]
    H. Hamann, A. Weger, J. Lacey, Z. Hu, P. Bose, E. Cohen, and J. Wakil, “Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements,” IEEE J. Solid-State Circuits, vol. 42, no. 1, Jan 2007, pp. 56–65.CrossRefGoogle Scholar
  17. [17]
    R. Ho, K. Mai, and M. Horowitz, “The Future of Wires,” Proceedings of the IEEE, vol. 89, no. 4, April 2001, pp. 490–504.Google Scholar
  18. [18]
    R. Ho, K. Mai, and M. Horowitz, “Managing Wire Scaling: A Circuit Perspective,” International Technology Conference, 2–4 June 2003, pp. 177–179.Google Scholar
  19. [19]
    N. James, P. Restle, J. Friedrich, B. Huott, and B. McCredie, “Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor,” ISSCC, 11–15 Feb 2007, pp. 298–604.Google Scholar
  20. [20]
    H. Mahmoodi, S. Mukhopadhayay, and K. Roy, “Estimation of Delay Variations Due to Random-Dopant Fluctuations in Nanoscale CMOS Circuits,” IEEE J. Solid-State Circuits, vol. 40, no. 9, Sept 2005, pp. 1787–1796.CrossRefGoogle Scholar
  21. [21]
    V. Mehrotra, S. L. Sam, D. Boning, A. Chandrakasan, R. Vallishayee, and S. Nassif, “A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance,” DAC, 5–9 June 2000, pp. 172–175.Google Scholar
  22. [22]
    S. Naffziger, B. Stackhouse, T. Grutkowski, D. Josephson, J. Desai, and M. Horowitz, “The Implementation of a 2-Core, Multi-Threaded Itanium Family Processor,” IEEE J. Solid-State Circuits, vol. 41, no. 1, Jan 2006, pp. 197–209.CrossRefGoogle Scholar
  23. [23]
    M. Nakai, S. Akui, K. Seno, N. Makai, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, “Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor,” IEEE J. Solid-State Circuits, vol. 40, no. 1, Jan 2005, pp. 28–35.CrossRefGoogle Scholar
  24. [24]
    M. Nakai, S. Akui, K. Seno, T Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, “Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor,” IEEE J. Solid-State Circuits, vol. 40, no. 1, Jan 2005, pp. 28–35.CrossRefGoogle Scholar
  25. [25]
    S. Nassif, “Delay Variability: Sources, Impacts and Trends,” ISSCC, 7–9 Feb 2000, pp. 368–369.Google Scholar
  26. [26]
    K. Nowka, G. Carpenter, and B. Brock, “The Design and Application of the PowerPC 405LP Energy-Efficient System-on-a-Chip,” IBM Journal of Research and Development, vol. 47, no. 5/6, Sept/Nov 2003, pp. 631–639.CrossRefGoogle Scholar
  27. [27]
    S.-I. Ochkawa, M. Aoki, and H. Masuda, “Analysis and Characterization of Device Variations in an LSI Chip Using an Integrated Device matrix Array,” IEEE Transactions on Semiconductor Manufacturing, vol. 17, no. 2, May 2004, pp. 155–165.CrossRefGoogle Scholar
  28. [28]
    R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, “Statistical Analysis of Subthreshold Leakage Current for VLSI Circuits,” IEEE Transactions on VLSI Systems, vol. 12, no. 2, Feb 2004, pp. 131–139.CrossRefGoogle Scholar
  29. [29]
    B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, Boston, 2001, pp. 550–556.Google Scholar
  30. [30]
    P. Restle, R. Frach, N. James, W. Huott, T. Skergan, S. Wilson, N. Schwartz, and J. Clabes, “Timing Uncertainty Measurements on the Power5 Microprocessor,” ISSCC, 15–19 Feb 2004, pp. 354–355.Google Scholar
  31. [31]
    M. Saint-Laurent and M. Swaminathan, “Impact of Power-Supply Noise on Timing in High-Frequency Microprocessors,” IEEE Transactions on Advanced Packaging, vol. 27, no. 1, Feb 2004, pp. 135–144.CrossRefGoogle Scholar
  32. [32]
    S. Samaan, “The Impact of Device Parameter Variations on the Frequency and Performance of VLSI Chips,” ICCAD, 7–11 Nov 2004, pp. 343–346.Google Scholar
  33. [33]
    A. Strak and H. Tenhunen, “Investigation of Timing Jitter in NAND and NOR Gates Induced by Power-Supply Noise,” ICECS, 10–13 Dec 2006, pp. 1160–1163.Google Scholar
  34. [34]
    H. Su, F. Liu, A. Devgan, E. Acar, and S. Nassif, “Full Chip Leakage-Estimation Considering Power Supply and Temperature Variations,” ISLPED, 25–27 Aug 2003, pp. 78–83.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Alan Drake

There are no affiliations available

Personalised recommendations