The Challenges of Testing Adaptive Designs

  • Eric Fetzer
  • Jason Stinson
  • Brian Cherkauer
  • Steve Poehlman
Part of the Series on Integrated Circuits and Systems book series (ICIR)

In this chapter, we describe the adaptive techniques used in the Itanium® 2 9000 series microprocessor previously known as Montecito [1].

Montecito features two dual-threaded cores with over 26.5 MB of total on die cache in a 90 nm process technology [ 2] with seven layers of copper interconnect. The die, shown in Figure 12.1, is 596 mm 2in size, contains 1.72 billion transistors, and consumes 104 W at a maximum frequency of 1.6 GHz. To manufacture a product of such complexity, a sophisticated series of tests are performed on each part to ensure reliable operation throughout its service at a customer installation. Adaptive features often interfere with these tests. This chapter discusses three adaptive features on Montecito: active de-skew for reliable low skew clocks, Cache Safe Technology® for robust cache operation, and Foxton Technology® for power management. Traditional test methods are discussed, and the specific impacts of active de-skew and the power measurement system for...


Delay Line Power Measurement Error Correction Code Soft Error Voltage Droop 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. [1]
    Naffziger, S., et al., “The Implementation of a 2-core Multi-Threaded Itanium-Family Processor,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 1–pp. 197–209, Jan. 2006CrossRefGoogle Scholar
  2. [2]
    Thompson, S., et al., “A 90 nm logic technology featuring 50 nm strained silicon channel transistor, 7 layers of Cu interconnects, low k ILD, and 1 μm2 SRAM cell,” Electron Devices Meeting, 2002. IEDM '02. Digest. International, pp. 61–64, Dec. 2002Google Scholar
  3. [3]
    Mahoney, P., Fetzer, E., et al., “Clock distribution on a dual-core, multi-threaded Itanium®-family processor,” Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International, Vol. 1, pp. 292–599, 6–10 Feb. 2005Google Scholar
  4. [4]
    Anderson, F.E., Wells, J.S., Berta, E.Z., “The core clock system on the next generation Itanium microprocessor,” Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International, Vol. 1, pp. 146–453, 3–7 Feb. 2002Google Scholar
  5. [5]
    Geannopoulos, G., Dai, X., “An adaptive digital deskewing circuit for clock distribution networks”, Solid-State Circuits Conference, 1998. Digest of Technical Papers. 45th ISSCC 1998 IEEE International, pp. 400–401, 5–7 Feb. 1998Google Scholar
  6. [6]
    Peterson, W.W., Weldon, E.J., Jr., Error-Correcting Codes, 2nd editions, MIT Press: Cambridge Mass., 1972zbMATHGoogle Scholar
  7. [7]
    Ziegler, J. F., Srinivasan, G. R., et al, “Terrestrial cosmic rays and soft errors,” IBM Journal of R and D, Vol. 40 No.1 1996Google Scholar
  8. [8]
    Ershov, M., Saxena, S., et al., “Dynamic recovery of negative bias temperature instability in p-type metal-oxide-semiconductor field-effect transistors,” Applied Physics Letters, , Vol. 83, No. 8, pp. 1647–1649, August 25 2003CrossRefGoogle Scholar
  9. [9]
    Agostinelli, M., et al., “Erratic fluctuations of SRAM cache Vmin at the 90 nm process technology node,” Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, pp. 655–658, Dec. 5 2005Google Scholar
  10. [10]
    McGowen, R., Poirier, C., et al., “Power and Temperature Control on a 90-nm Itanium Microprocessor,” Solid-State Circuits, IEEE Journal of Vol. 41, No. 1, pp. 229–237, Jan. 2006Google Scholar
  11. [11]
    Wayne Needham, Cheryl Prunty, Eng Hong Yeoh, “High Volume Microprocessor Test Escapes, An Analysis Of Defects Our Test Are Missing”, IEEE International Test Conference, pp. 25–34, 1998.Google Scholar
  12. [12]
    Mike Mayberry, John Johnson, Navid Shahriari, Mike Trip, “Realizing the Benefits of Structural Test For Intel Microprocessors”, IEEE International Test Conference, pp. 456–463, 2002.Google Scholar
  13. [13]
    Ismet Bayraktaroglu, Jim Hunt, Daniel Watkins, “Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues”, IEEE International Test Conference Conference, 2006.Google Scholar
  14. [14]
    Huston, R., “Microprocessor Functional Test Generation on the Sentry 600”, IEEE International Test Conference, 1974.Google Scholar
  15. [15]
    Praveen Parvathala, Kailas Maneparambil, William Lindsay, “ FRITS – A Microprocessor Functional BIST Method”, IEEE International Test Conference, pp. 590–598, 2002.Google Scholar
  16. [16]
    Krantis, N., Xenoulis, G., Paschalis, A., Gizopoulos, D., Zorian, Y., “Application and Analysis of RT-Level Software-Based Self-testing for Embedded Processor Cores”, IEEE Intetrnational Test C440.Google Scholar
  17. [17]
    Wei-Cheng Lai, Kwang-Ting Cheng, “Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip”, Design Automation Conference ,pp. 59–64, 2001.Google Scholar
  18. [18]
    Tsang, J., et. al., “Picosecond imaging circuit analysis”, IBM Journal of Research and Development, Vol. 44, No. 4, pp. 583–603, 2000.CrossRefGoogle Scholar
  19. [19]
    Leon, A. S., et al., “A Power-Efficient High-Throughput 32-Thread SPARC Processor,” IEEE J. Solid-State Circuits, Vol. 42, No. 1, pp. 7–16, Jan. 2007.CrossRefGoogle Scholar
  20. [20]
    Harry Hsiung, “Manufacturing and test Solutions with EFI”, Intel Developers Forum, 2003.Google Scholar
  21. [21]
    Peter Maxwell, Ismed Hartanto, Lee Bentz, “Comparing Functional and Structural Tests”, IEEE International Test Conference, pp. 400–407, 2000.Google Scholar
  22. [22]
    Satish M. Thatte, Jacob A. Abraham, “Test Generation For Microprocessors”, IEEE Transactions On Computers, Vol. 29, No. 6, pp. 429–441.Google Scholar
  23. [23]
    Advanced Configuration and Power Interface Specification, rev 3.0b,, October 2006

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • Eric Fetzer
  • Jason Stinson
  • Brian Cherkauer
  • Steve Poehlman

There are no affiliations available

Personalised recommendations