Dynamic and Adaptive Techniques in SRAM Design

  • John J. Wuu
Part of the Series on Integrated Circuits and Systems book series (ICIR)


The International Technology Roadmap for Semiconductors (ITRS) predicted in 2001 that by 2013, over 90% of SOC die area will be occupied by memory [7]. Such level of integration poses many challenges, such as power, reliability, and yield. In addition, as transistor dimensions continue to shrink, transistor threshold voltage (VT) variation, which is inversely proportional to the square root of the transistor area, continues to increase. This VTvariation, along with other factors contributing to overall variation, is creating difficulties in designing stable SRAM cells that meet product density and voltage requirements.

This chapter examines various dynamic and adaptive techniques for mitigating some of these common challenges in SRAM design. The chapter first introduces innovations at the bitslice level, which includes SRAM cells and immediate peripheral circuitry. These innovations seek to improve bitcell stability and increase the read and write margins, while reducing...


Source Line Power Saving Error Correct Code Storage Node Read Operation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  • John J. Wuu
    • 1
  1. 1.Advanced Micro Devices, Inc.USA

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