As the electronic design automation (EDA) industry focuses on design-for-manufacturability (DFM), the older problem of design-for-test has almost been forgotten. But ICs built at 90 nanometers and below pose new and com-plex challenges for design-for-testability (DFT) tools and techniques. At those geometries, small delay defects become a major contributor to chip failures, but they can't be detected by conventional automatic test pattern generation (ATPG) tools since they are timing unaware. Low-power ICs, which will in-clude most chips at 65nm technology node, demand new approaches to low power scan design and pattern generation. Test data run over many dice and wafers can provide valuable diagnostic information that helps foundries and designers ramp up their yields. In this sense, DFT meets DFM and becomes a critical element in the attempt to mitigate process variability.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
1. International Technology Roadmap for Semiconductors 2006 edition.
2. T. M. Mak, A. Krstic, K. T. Cheng and L. C. Wang, “New challenges in delay testing of nanometer, multigigahertz designs,” IEEE Design & Test of Computers, vol. 21, no. 3, May-June 2004, pp. 241 - 248.
3. K. Roy, K. T. Cheng and T.M. Mak, “Test Consideration for Nanometer-Scale CMOS Circuits,” IEEE Design & Test of Computers, pp. 128-136, 2006.
K. Kim, S. Mitra and P.G. Ryan, “Delay Defect Characteristics and Testing Strategies,” IEEE Design & Test of Computers, vol. 20, no. 5, Sept.-Oct. 2003 pp. 816
5. R. Wilson, “Delay-Fault Testing Mandatory, Author Claims,” EE Design, Dec. 2002.
M. Tehranipour, N. Ahmed and M. Nourani, “Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture,” IEEE Transactions on CAD, vol. 23, issue 5, pp. 800–811, May 2004.
7. M. Cuviello, S. Dey, X. Bai, and Y. Zhao, “Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects,” in Proc. Int. Conf. Computer-Aided Design (ICCD’99), pp. 297-303, 1999.
8. A. Sinha, S. K. Gupta, and M. A. Breuer, “Validation and Test Issues Related to Noise Induced Byparasitic Inductances of VLSI Interconnects,” IEEE Trans. Adv. Packaging, pp. 329339, 2002.
9. W. Chen, S. Gupta, and M. Breuer, “Test Generation for Crosstalk-Induced Delay in Integrated Circuits,” in Proc. Int. Test Conf. (ITC’99), pp. 191200, 1999.
10. M. Nourani, M. Tehranipoor and N. Ahmed, “Pattern Generation and Estimation for Power Supply Noise Analysis,” in proc. IEEE VLSI Test Symposium (VTS’05), pp. 439-444, 2005
11. S. Zhao and K. Roy, “Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits,” in Proc. Thirteenth Int. Conf. on VLSI Design,, pp. 168-173, 2000.
12. N. Ahmed, M. Tehranipoor and V. Jayaram, “Timing-Based Delay Test for Screening Small Delay Defects,” in Proc. Design Automation Conference (DAC06), pp. 320-325, 2006
13. N. Ahmed, M. Tehranipoor and V. Jayaram, “A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-Drop Effects,” in Proc. Int. Conf. on Computer-Aided Design (ICCAD’06), 2006.
14. X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson and N. Tamarapalli, “High-Frequency, At-Speed Scan Testing,” IEEE Design & Test of Computers, pp. 17-25, Sep-Oct 2003.
15. B. Kruseman, A. K. Majhi, G. Gronthoud and S. Eichenberger, “On hazard-free patterns for fine-delay fault testing,” in Proc. Int. Test Conf. (ITC’04), pp. 213-222, 2004.
“Designing Reliable Systems from Unreliable Components: The Challenges of Transistor variability and Degradation,” IEEE Micro, vol. 25, no. 6, Nov.-Dec. 2005, pp. 10–16.
17. A. Agarwal, D. Blaauw, V. Zolotov “Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations,” in Proc. Int. Conf. on Computer-Aided Design, pp. 900-907, 2003.
18. D. Blaauw and S. Nassif, “Static Performance Analysis under Process and Environment Variations,” http://domino.research.ibm.com/acas.
19. K. Agarwal, D. Sylvester, D. Blaauw, Frank Liu, S. Nassif, and S. Vrudhula, “Variational Delay Metrics for Interconnect Timing Analysis,” in Proc. Design Automation Conference (DAC’04), pp. 381-384, 2004.
20. J. Le, X. Li, and L. Pileggi, “VSTAC: Statistical Timing Analysis with Correlation,” in Proc. Design Automation Conference (DAC’04), pp. 343-348, 2004.
21. B. F. Romanescu, M. E. Bauer, S. Ozev and D. J. Sorin, “VariaSim: Simulating Circuits and Systems in the Presence of Process Variability,” Technical Report, DUKEECE, no. 2007-3, June, 2007
Z. Lin, C. Spanos, L. Milor, Y. Lin, “Circuit Sensitivity to Interconnect Variation,” IEEE Trans. on Semiconductor Manufacturing, vol. 11, no. 4, 557–568, 1998.
23. A. Agarwal, D. Blaauw, V. Zolotov “Statistical Clock Skew Analysis Considering Intra-Die Process Variations,” in Proc. Int. Conf. on Computer-Aided Design, pp. 914-921, 2003.
24. V. Mehrotra and D. Boning, “Technology Scaling Impact of Variation on Clock Skew and Interconnect Delay,” in Proc. Intl. Interconnect Tech. Conf., pp. 122-124,2001.
25. Cadence Inc., “http://www.cadence.com,”, 2005.
Further Reading
26. L. Wang, P. Bastani, M. S. Abadir, “Design-Silicon Timing Correlation A Data Mining Perspective,” in Proc. IEEE Design Automation Conference, pp. 384-389, 2007.
27. B. N. Lee, L. C. Wang, M. S. Abadir, “Refined statistical static timing analysis through learning spatial delay correlations,” in Proc. Design Automation Conference, 2006.
28. L. C. Wang; T. M. Mak, K. T. Cheng, M. S. Abadir, “On path-based learning and its applications in delay test and diagnosis,” in Proc. Design Automation Conference, 2004.
29. L. C. Wang, “Regression simulation: applying path-based learning in delay test and post-silicon validation,” in Proc. Design, Automation and Test in Europe Conference, vol. 1, pp. 692-693, 2004.
30. R. Putman, R. Gawde, “Enhanced timing-based transition delay testing for small delay defects,” in Proc. VLSI Test Symposium, 2006.
31. Y. Sato, S. Hamada, T. Maeda, A. Takatori, Y. Nozuyama, S. Kajihara, “Invisible delay quality - SDQM model lights up what could not be seen,” in Proc. Int. Test Conference, 2005.
M. Kumar and S. Tragoudas, “High-Quality Transition Fault ATPG for Small Delay Defects,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 5, pp. 983–9.
33. X. Lin; K. Tsai; M. Kassab, J. Rajski, T. Kobayashi, R. Klingenberg, R. Klingenberg; Y. Sato, S. Hamada, T. Aikyo, “Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects,” in Proc. Asian Test Symposium, pp. 139-146, 2006.
34. V. Kumar, S. Tragoudas, “Quality transition fault tests suitable for small delay defects,” in Proc. Int. Conf. on Computer Design, pp. 468-470, 2005.
35. S. Hamada, T. Maeda, A. Takatori, Y. Noduyama, Y. Sato, “Recognition of Sensitized Longest Paths in Transition Delay Test,” in Proc. Int. Test Conference, pp. 1-6, 2006.
36. H. Yan and A. Singh, “Evaluating the effectiveness of detecting delay defects in the slack interval: a simulation study,” in Proc. Int. Test Conference, pp. 242-251, 2004.
37. B. Kruseman, A. Majhi, G. Gronthoud, S. Eichenberger, “On hazard-free patterns for fine-delay fault testing,” in Proc. Int. Test Conference, pp. 213-222, 2004.
38. M. Favalli and C. Metra, “Pulse propagation for the detection of small delay defects,” in Proc. Design, Automation & Test in Europe Conference & Exhibition, pp. 1-6, 2007.
39. R. Tayade, S. Sundereswaran and J. Abraham, “Small-Delay Defect Detection in the Presence of Process Variations,” in Proc. Int. Symp. on Quality Electronic Design, pp. 711-716, 2007.
40. K. T. Cheng and H. C. Chen, “Generation of High Quality Non-Robust Tests for Path Delay Faults,” in Proc. Design Automation Conference, pp. 365-369, 1994.
41. H. Yan and A. Singh, “A delay test to differentiate resistive interconnect faults from weak transistor defects,” in Proc. Int. Conf. on VLSI Design, pp. 47-52, 2005.
42. K. L. Shepard and V. Narayanan, “Noise in Deep Submicron Digital Design,” in Proc. IEEE Int. Conf. on Computer Aided Design (ICCAD), pp. 524-531, 1996.
43. N. Ahmed, M. Tehranipoor and V. Jayaram, “Supply Voltage Noise Aware ATPG for Transition Delay Faults,” IEEE VLSI Test Symposium (VTS), 2007.
44. N. Ahmed, M. Tehranipoor and V. Jayaram, “Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design,” Design Automation Conf. (DAC), 2007.
45. S. Pant, D. Blaauw, V. Zolotov, S. Sundareswaran and R. Panda, “Vectorless Analysis of Supply Noise Induced Delay Variation,” in Proc. IEEE Int. Conf. on Computer Aided Design (ICCAD), pp.184-191, 2003.
46. J. Wang, Z. Yue, X. Lu, W. Qiu, W. Shi, and D. Walker, “A vector-based approach for power supply noise analysis in test compaction,” in Proc. Int. Test Conf. (ITC), 2005.
47. J. Wang, X. Lu, W. Qiu, Z. Yue, S. Fancler, W. Shi, and D. Walker, “Static compaction of delay tests considering power supply noise,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 235240, 2005.
48. R. Ahmadi and F. N. Najm, “Timing Analysis in Presence of Power Supply and Ground Voltage Variations,” in IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, Nov. 2003, pp. 176-183.
A. Muhtaroglu, G. Taylor, and T. Rahal-Arabi, “On-die droop detector for analog sensing of power supply noise,” Jour. of SolidState Circuits, vol. 39, no. 4, pp. 651–660, 2004.
50. Z. Abuhamdeh, B. Hannagan, J. Remmers and A. Crouch, “Consideration For a Production IR-Drop Screen On A Chip,” IEEE Design & Test of Computers, May-June 2007.
51. P. Ghanta and S. Vrudhula, “Analysis of Power Supply Noise in the Presence of Process Variations,” IEEE Design & Test of Computers, May-June 2007.
I. Pomeranz and S. M. Reddy, “An Efficient Nonenumerative Method to Estimate the Path Delay Fault Coverage in Combinational Circuits,” IEEE Transactions on Computer-Aided Design, vol. 13, no. 2, Feb. 1994, pp. 240–250.
Rights and permissions
Copyright information
© 2008 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
(2008). At-speed Test Challenges for Nanometer Technology Designs. In: Nanometer Technology Designs High-Quality Delay Tests. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-75728-5_2
Download citation
DOI: https://doi.org/10.1007/978-0-387-75728-5_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-76486-3
Online ISBN: 978-0-387-75728-5
eBook Packages: EngineeringEngineering (R0)