This chapter presents an automatic pattern generation methodology to stimulate the maximum power supply noise in deep submicron CMOS circuits. This information can benefit both the design and failure anaysis teams. The generated test patterns can also be used for targeting supply noise effects during fabrication test. The design team can use this information to further analyze the power/ground network for driving maximum current to the circuit without affecting the circuit performance.
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(2008). Pattern Generation for Power Supply Noise Analysis. In: Nanometer Technology Designs High-Quality Delay Tests. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-75728-5_10
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DOI: https://doi.org/10.1007/978-0-387-75728-5_10
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