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Emerging Nanotechnologies pp 339–372Cite as

Towards Nanoelectronics Processor Architectures

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Part of the book series: Frontiers in Electronic Testing ((FRET,volume 37))

CMOS technology has moved beyond 80 nanometers in scale, and according to the International Technology Roadmap for Semiconductors (ITRS), is projected to reach beyond 22 nanometers in the next several years [1, 2]. At nanometer scale, CMOS devices start to meet the physical limits and further shrinking in the CMOS feature sizes is checkmated by the insurmountable barriers of quantum effects, leakage current and power consumption.

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Authors and Affiliations

  1. University of California, San Diego

    W. Rao & A. Orailoglu

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  1. W. Rao
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  2. A. Orailoglu
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  3. R. Karri
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Editor information

Editors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT 06269, USA

    Mohammad Tehranipoor

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Rao, W., Orailoglu, A., Karri, R. (2008). Towards Nanoelectronics Processor Architectures. In: Tehranipoor, M. (eds) Emerging Nanotechnologies. Frontiers in Electronic Testing, vol 37. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-74747-7_13

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  • DOI: https://doi.org/10.1007/978-0-387-74747-7_13

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