Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint

  • Erik Larsson
  • Stina Edbom
Conference paper
Part of the IFIP International Federation for Information Proc book series (IFIPAICT, volume 240)

Testing is used to ensure high quality chip production. High test quality implies the application of high quality test data; however, the technology development has lead to a need of an increasing test data volume to ensure high test quality. The problem is that the test data volume has to fit the limited memory of the ATE (Automatic Test Equipment). In this paper, we propose a test data truncation scheme that for a modular core-based SOC (Systemon- Chip) selects test data volume in such a way that the test quality is maximized while the selected test data is guaranteed to met the ATE memory constraint. We define, for each core as well as for the system, a test quality metric that is based on fault coverage, defect probability and number of applied test vectors. The proposed test data truncation scheme selects the appropriate number of test vectors for each individual core based on the test quality metric, and schedules the transportation of the selected test data volume on the Test Access Mechanism such that the system’s test quality is maximized and the test data fits the ATE’s memory. We have implemented the proposed technique and the experimental results, produced at reasonable CPU times, on several ITC’02 benchmarks show that high test quality can be achieved by a careful selection of test data. The results indicate that the test data volume (test application time) can be reduced to about 50% while keeping a high test quality.

References

  1. 1.
    Chandra and K. Chakrabarty, “System-on-a-Chip Test Data Compression and Decompression Architectures Based on Golomb Codes”, Transactions on CAD of IC and Systems, pp. 355-367, Vol. 20, No. 3, 2001.CrossRefGoogle Scholar
  2. 2.
    Chandra and K. Chakrabarty, “Frequency -Directed-Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression”, Proceedings of VLSI Test Symposium (VTS), pp. 42-47, 2001.Google Scholar
  3. 3.
    G. Blom, “Sannolikhetsteori och statistikteori med tillŠ mpningar”, Studentlitteratur, 1989.Google Scholar
  4. 4.
    S. Edbom and E. Larsson, “An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint”, Proceedings of Asian Test Symposium (ATS), pp. 254-257, 2004.Google Scholar
  5. 5.
    S. K. Goel, K. Chiu, E. J. Marinissen, T. Nguyen, and S. Oostdijk, “Test Infrastructure Design for the NexperiaTMHome Platform PNX8550 System Chip”, Proceedings of Design, Automation and Test in Europe Conference (DATE), pp. 1530-1591, Paris, France, 2004.Google Scholar
  6. 6.
    P. Harrod, “Testing reusable IP-a case study”, Proceedings of International Test Conference (ITC), pp. 493-498, Atlantic City, NJ, USA, 1999.Google Scholar
  7. 7.
    S. D. Huss and R. S. Gyurcsik, “Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time”, Proceedings of Design Automation Conference (DAC), pp. 494-499, 1991.Google Scholar
  8. 8.
    H. Ichihara, A. Ogawa, T. Inoue, and A. Tamura, “Dynamic Test Compression Using Statistical Coding”, Proceedings of Asian Test Symposium (ATS), pp. 143-148, Kyoto, Japan, November 2001.Google Scholar
  9. 9.
    V. Iyengar, K. Chakrabarty, and E. J. Marinissen, “Test wrapper and test access mechanism co-optimization for system-on-chip”, Proceedings of International Test Conference (ITC), pp. 1023-1032, Baltimore, MD, USA, 2001.Google Scholar
  10. 10.
    V. Iyengar, K. Chakrabarty, and B. Murray, “Built-In Self-Testing of Sequential Corcuits Using Precomputed Test Sets”, Proceedings of VLSI Test Symposium (VTS), pp. 418-423, 1998.Google Scholar
  11. 11.
    V. Iyengar, S. K. Goel, E. J. Marinissen, and K. Chakrabarty, “Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints”, Proceedings of International Test Conference (ITC), pp. 1159-1168, Baltimore, USA, October 2002.Google Scholar
  12. 12.
    W. J. Jiang and B. Vinnakota, “Defect-Oriented Test Scheduling”, Transactions on Very-Large Scale Integration (VLSI) Systems, Vol. 9, No. 3, pp. 427-438, June 2001.CrossRefGoogle Scholar
  13. 13.
    S. Koranne, “On Test Scheduling for Core-Based SOCs”, Proceedings of International Conference on VLSI Design (VLSID), pp. 505-510, Bangalore, India, January 2002.Google Scholar
  14. 14.
    E. Larsson, J. Pouget, and Z. Peng, “Defect-Aware SOC Test Scheduling“, Proceedings of VLSI Test Symposium (VTS), Napa Valley, CA, USA, pp. 359-364, April 2004.CrossRefGoogle Scholar
  15. 15.
    T.L. McLaurin and J.C. Potter, “On-the-Shelf Core Pattern Methodology for ColdFire(R) Microprocessor Cores”, Proceedings of International Test Conference (ITC), pp. 1100-1107, 2000.Google Scholar
  16. 16.
    E. J. Marinissen, R. Arendsen, G. Bos, H. Dingemanse, M. Lousberg, and C. Wouters, “A structured and scalable mechanism for test access to embedded reusable cores”, Proceedings of International Test Conference (ITC), pp. 284-293, Washington, DC, USA, October 1998.Google Scholar
  17. 17.
    E. J. Marinissen, V. Iyengar, and K. Chakrabarty, “A Set of Benchmarks for Modular Testing of SOCs”, Proceedings of International Test Conference (ITC), pp. 519-528, Baltimore, MD, USA, October 2002.Google Scholar
  18. 18.
    L. Milor and A. L. Sangiovanni-Vincentelli, “Minimizing Production Test Time to Detect Faults in Analog Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., Vol. 13, No. 6, pp 796-, June 1994.CrossRefGoogle Scholar
  19. 19.
    P. Varma and S. Bhatia, “A Structured Test Re-Use Methodology for Core-based System Chips”, Proceedings of International Test Conference (ITC), pp. 294-302, Washington, DC, USA, October 1998.Google Scholar
  20. 20.
    E. H. Volkerink, A. Khoche, and S. Mitra, “Packet-based Input Test Data Compression Techniques”, Proceedings of International Test Conference (ITC), pp. 154-163, Baltimore, MD, USA, October 2002.Google Scholar
  21. 21.
    H. Vranken, F. Hapke, S. Rogge, D. Chindamo, and E. Volkrink, “ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume”, Proceedings of International Test Conference (ITC), pp. 1069-1078, Charlotte, NC, USA, 2003.Google Scholar
  22. 22.
    E. Larsson and S. Edbom, “Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint”, pp. 429-434, IFIP VLSISOC 2005, Perth, Australia, October 17-19, 2005.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Erik Larsson
    • 1
  • Stina Edbom
    • 1
  1. 1.Department of Computer and Information ScienceLinköpings UniversitetSweden

Personalised recommendations