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A Traffic Injection Methodology with Support for System-Level Synchronization

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Part of the IFIP International Federation for Information Proc book series (IFIPAICT,volume 240)

In highly parallel Multi-Processor System-on-Chip (MPSoC) design stages, interconnect performance is a key optimization target. To effectively achieve this objective, true-to-life IP core traffic must be injected and analyzed. However, the parallel development of MPSoC components may cause IP core models to be still unavailable when tuning communication performance. Traditionally, synthetic traffic generators have been used to overcome such an issue. However, target applications increasingly present non-trivial execution flows and synchronization patterns, especially in presence of underlying operating systems and when exploiting interrupt facilities. This property makes it very difficult to generate realistic test traffic. This paper presents a selection of application flows, representative of a wide class of applications with complex interruptbased synchronization; a reference methodology to split such applications in execution subflows and to adjust the overall execution stream based upon hardware events; a reactive simulation device capable of correctly replicating such software behaviours in the MPSoC design phase. Additionally, we validate the proposed concept by showing cycle-accurate reproduction of a previously traced application flow.


  • Execution Trace
  • Program Counter
  • Design Automation Conference
  • Interrupt Handling
  • 38th Design Automation

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  1. The Real-Time Operating System for Multiprocessor Systems.

  2. Open Core Protocol Specification, Release 2.0, 2003.

    Google Scholar 

  3. F. Angiolini, S. Mahadevan, J. Madsen, L. Benini, and J. Sparsø. Realistically rendering SoC traffic patterns with interrupt awareness. In IFIP International Conference on Very Large Scale Integration (VLSI-SoC), September 2005.

    Google Scholar 

  4. L. Cai and D. Gajski. Transaction level modeling in system level design. CECS technical report 03-10, Center for Embedded Computer Systems, Information and Computer Science, University of California, Irvine, March 2003.

    Google Scholar 

  5. F. Fummi, P. Gallo, S. Martini, G. Perbellini, M. Poncino, and F. Ricciato. A timing-accurate modeling and simulation environment for networked embedded systems. In Proceedings of the 42th Design Automation Conference (DAC), pages 42-47, June 2003.

    Google Scholar 

  6. T. Gr ötker, S. Liao, G. Martin, and S. Swan. System Design with SystemC. Kluwer Academic Publishers, 2002.

    Google Scholar 

  7. S. Kuenzli, F. Poletti, L. Benini, and L. Thiele. Combining simulation and formal methods for system-level performance analysis. In Proceedings of Design, Automation and Testing in Europe Conference 2006 (DATE), pages 236-242. IEEE, March 2006.

    Google Scholar 

  8. K. Lahiri, A. Raghunathan, and S. Dey. Evaluation of the traffic-performance characteristics of System-on-Chip communication architectures. In Proceedings of the 14th International Conference on VLSI Design, pages 29-35, 2001.

    Google Scholar 

  9. M. Loghi, F. Angiolini, D. Bertozzi, L. Benini, and R. Zafalon. Analyzing on-chip communication in a MPSoC environment. In Proceedings of the Design, Automation and Test in Europe Conference (DATE). IEEE, 2004.

    Google Scholar 

  10. S. Mahadevan, F. Angiolini, M. Storgaard, R. G. Olsen, J. Sparsø, and J. Madsen. A network traffic generator model for fast network-on-chip simulation. In Proceedings of Design, Automation and Testing in Europe Conference 2005 (DATE), pages 780-785. IEEE, March 2005.

    Google Scholar 

  11. O. Ogawa, S. B. de Noyer, P. Chauvet, K. Shinohara, Y. Watanabe, H. Niizuma, T. Sasaki, and Y. Takai. A practical approach for bus architecture optimization at transaction level. In Proceedings of Design, Automation and Testing in Europe Conference 2004 (DATE). IEEE, March 2003.

    Google Scholar 

  12. S. Pasricha, N. Dutt, and M. Ben-Romdhane. Extending the transaction level modeling approach for fast communication architecture exploration. In Proceedings of 38th Design Automation Conference (DAC), pages 113-118. ACM, 2004.

    Google Scholar 

  13. L. Schaelicke, A. Davis, and S. A. McKee. Profiling IO interrupts in modern architectures. In Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE, 2000.

    Google Scholar 

  14. M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli. Addressing the System-on-Chip interconnect woes through communication-based design. In Proceedings of the 38th Design Automation Conference (DAC’01), pages 667-672, June 2001.

    Google Scholar 

  15. W. Wolf. Computers as Components:Principles of Embedded Computing System Design, chapter 3. Morgan Kaufmann, 2001.

    Google Scholar 

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Mahadevan, S., Angiolini, F., Sparsø, J., Benini, L., Madsen, J. (2007). A Traffic Injection Methodology with Support for System-Level Synchronization. In: Reis, R., Osseiran, A., Pfleiderer, HJ. (eds) Vlsi-Soc: From Systems To Silicon. IFIP International Federation for Information Proc, vol 240. Springer, Boston, MA.

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  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-73660-0

  • Online ISBN: 978-0-387-73661-7

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