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Abstract

There are several concepts of how to verify the correctness of a circuit. Since designing and manufacturing integrated circuits are very time-consuming and expensive tasks it is necessary to detect errors as soon as possible in order to avoid additional costs (e.g., see [9.2]).

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References

  1. Eveking, E.; Hinrichsen, H.; Ritter, G.: ‘Automatic Verification of Scheduling Results in High-Level Synthesis.’ DATE’99, 1999

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  2. Fournier, L.; Arbetman, Y.; Levinger, M.: ‘Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator.’ DATE’99, 1999

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  3. Hendricx, S.; Claesen, L.: ‘Formally Verified Redundancy Removal.’ DATE’99, 1999

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  4. Lipsett, R.; Schaefer, C.; Ussery, C.: ‘VHDL: Hardware Description and Design.’ Kluwer Academic Publishers, 1989

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  5. Ten Hagen, K.: ‘Abstrakte Modellierung digitaler Schaltungen.’ Berlin: Springer Verlag, 1995

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© 2003 Springer Science+Business Media New York

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RĂ¼lling, W. (2003). Circuit Verification. In: Jansen, D. (eds) The Electronic Design Automation Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-73543-6_9

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  • DOI: https://doi.org/10.1007/978-0-387-73543-6_9

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5369-8

  • Online ISBN: 978-0-387-73543-6

  • eBook Packages: Springer Book Archive

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