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Accellera C/C++ Working Group of the Architectural Language Committee. RTL Semantics, Draft Specification. Technical report, Accellera, February 2001. available at http://www.eda.org/alc-cwg/cwg-open.pdf .
R. Dömer, A. Gerstlauer, and D. Shin. Cycle-accurate RTL modeling with multi-cycled and pipelined components. In Proceedings of International SoC Design Conference, pages 375-378, October 2006.
D. D. Gajski, N. Dutt, S. Y.-L. Lin, and A. Wu. High Level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, 1992.
D. D. Gajski, J. Zhu, R. Dömer, A. Gerstlauer, and S. Zhao. SpecC: Specification Language and Methodology. Kluwer Academic Publishers, January 2000.
A. Gerstlauer, L. Cai, D. Shin, R. Dömer, and D. D. Gajski. System-on-Chip component models. Technical Report CECS-TR-03-26, Center for Embedded Computer Systems, University of California, Irvine, August 2003.
T. Grötker, S. Liao, G. Martin, and S. Swan. System Design with SystemC. Kluwer Academic Publishers, March 2002.
S. Gupta. SPARK: High-level synthesis using parallelizing compiler techniques. available at http://www.cecs.uci.edu/∼spark/.
A. A. Jerraya, I.-C. Park, and K. O’Brien. AMICAL: An interactive high level synthesis environment. In Proceedings of the European Design Automation Conference, pages 58-62, February 1993.
H.-P. Juan, D. D. Gajski, and V. Chaiyakul. Clock-driven performance optimization in interactive behavioral synthesis. In Proceedings of the International Conference on Computer-Aided Design, pages 154-157, November 1996.
D. Ku and G. D. Micheli. High-level Synthesis of ASICs under Timing and Synchronization Constraints. Kluwer Academic Publishers, 1992.
B. Landwehr, P. Marwedel, and R. Dömer. OSCAR: Optimum simultaneous scheduling, allocation and resource binding based on integer programming. In Proceedings of the European Design Automation Conference, February 1994.
Catapult C Synthesis, Mentor Graphics Inc. available at http://www.mentor.com/.
L. Séméria and G. D. Micheli. SpC: Synthesis of pointers in C, application of pointer analysis to the behavioral synthesis from C. In Proceedings of the International Conference on Computer-Aided Design, pages 340-346, November 1998.
D. Shin and D. D. Gajski. Scheduling in RTL design methodology. Technical Report CECS-TR-02-11, Center for Embedded Computer Systems, University of California, Irvine, April 2002.
Behavioral Compiler, Synopsys Inc. available at http://www.synopsys.com/.
K. Wakabayashi and T. Okamoto. C-based SoC design flow and EDA tools: An ASIC and system vender perspective. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2000.
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Shin, D., Gerstlauer, A., Dömer, R., Gajski, D.D. (2007). An Interactive Design Environment for C-based High-Level Synthesis. In: Rettberg, A., Zanella, M.C., Dömer, R., Gerstlauer, A., Rammig, F.J. (eds) Embedded System Design: Topics, Techniques and Trends. IFIP – The International Federation for Information Processing, vol 231. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-72258-0_12
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