BSIM-CMG: A Compact Model for Multi-Gate Transistors
This Chapter describes the physics behind the BSIM-CMG (Berkeley Short-channel IGFET Model – Common Multi-Gate) compact models for multigate MOSFETs. A compact model serves as a link between process technology and circuit design. It is a concise mathematical description of the device physics in the transistor. Some simplifications in the physics, however, can be made to enable fast computer analysis of device/circuit behavior.
The scaling of conventional planar CMOS is expected to become increasingly difficult due to increasing gate leakage and subthreshold leakage.[1-2] Multi-gate FETs such as FinFETs have emerged as the most promising candidates to extend the CMOS scaling into the sub-25nm regime.[3-4] The strong electrostatic control over the channel originating from the use of multiple gates reduces the coupling between source and drain in the subthreshold region and it enables the Multigate transistor to be scaled beyond bulk planar CMOS for a given dielectric thickness. Numerous efforts are underway to enable large scale manufacturing of multi-gate FETs. At the same time, circuit designers are beginning to design and evaluate multi-gate FET circuits.
A compact model serves as a link between process technology and circuit design. It is a concise mathematical description of the complex device physics in the transistor. A compact model maintains a fine balance between accuracy and simplicity. An accurate model stemming from physics basis allows the process engineer and circuit designer to make projections beyond the available silicon data (scalability) for scaled dimensions and also enables fast circuit/device co-optimization. The simplifications in the physics enable very fast analysis of device/circuit behavior when compared to the much slower numerical based TCAD simulations. It is thus necessary to develop a compact model of multi-gate FETs for technology/circuit development in the short term and for product design in the longer term.
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