Tool Compatibility Gotchas

  • Stuart Sutherland
  • Don Mills
Chapter

Abstract

Time in Verilog is a 64-bit unsigned integer. Delays are specified by using a hash mark (#) followed by a number. A delay does not have any indication of what unit of time is being represented.

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References

  1. 1.
    SystemVerilog 3.1a Language Reference Manual: Accellera’s Extensions to Verilog, Copyright 2004 by Accellera Organization, Inc., Napa, CA, http://www.eda.org/sv/SystemVerilog_3.1a.pdf.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Stuart Sutherland
    • 1
  • Don Mills
    • 2
  1. 1.Sutherland HDL, Inc.TualatinUSA
  2. 2.LCDM EngineeringChandlerUSA

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