Time in Verilog is a 64-bit unsigned integer. Delays are specified by using a hash mark (#) followed by a number. A delay does not have any indication of what unit of time is being represented.
KeywordsRandom Number Generator Procedural Block Verification Code Tool Vendor Delay Time Unit
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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- 1.SystemVerilog 3.1a Language Reference Manual: Accellera’s Extensions to Verilog, Copyright 2004 by Accellera Organization, Inc., Napa, CA, http://www.eda.org/sv/SystemVerilog_3.1a.pdf.Google Scholar
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