A common verification gotcha is not understanding the event scheduling of initial and always procedural blocks. Because of the name “initial”, some engineers assume that initial blocks are executed before always blocks. Other engineers believe just the opposite is true, that initial blocks are guaranteed to execute after all always blocks are active.
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- 1.Understanding Verilog Blocking and Nonblocking Assignments, by Stuart Sutherland. Published in the proceedings of International Cadence Users Group, San Jose, 1996. Also available at from the author’s web site, http://www.sutherland.com/papers.htmlGoogle Scholar