RTL Modeling Gotchas

  • Stuart Sutherland
  • Don Mills
Chapter

Abstract

Synthesizable RTL modeling style requires that Verilog always procedural blocks have an edge sensitive timing control (the @ token) following the always keyword. This time control is referred to as the block’s sensitivity list.

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References

  1. 1.
    Being Assertive With Your X, by Don Mills. Published in the proceedings of SNUG San Jose, 2004. Also available from the author’s web site, http://www.lcdm-eng.com/assertiveX.pdf.Google Scholar
  2. 2.
    SystemVerilog Assertions are for Design Engineers, Too, by Don Mills and Stuart Sutherland. Published in the proceedings of SNUG San Jose, 2006. Also available from the author’s web site, http://www.sutherland.com/papers.html.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Stuart Sutherland
    • 1
  • Don Mills
    • 2
  1. 1.Sutherland HDL, Inc.TualatinUSA
  2. 2.LCDM EngineeringChandlerUSA

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