Declaration and Literal Number Gotchas

Abstract

An identifier in Verilog and SystemVerilog is the user-specified name of some object, such as the name of a module, wire, variable, or function. Verilog and System Verilog are case-sensitive languages, meaning that lowercase letters and uppercase letters are perceived as different in identifiers and in keywords. Keywords are always in all lowercase letters. User-created identifiers can use a mix of lowercase and uppercase letters, as well as numbers and the special characters _, $, and \ (the latter is an escape character).

Note: the code examples in this chapter are contrived in order to illustrate each gotcha using small examples. In real design and verification code, these gotchas might not be as obvious or easy to debug.