In this chapter, we propose a placement tool called Dragon which deploys hierarchical techniques to place large-scale mixed size designs that may contain thousand of macro blocks and millions of standard cells [1–3]. Min-cut-based top-down approach is taken to handle the large complexity of designs and simulated annealing is used to minimize the total wire length. Min-cut partitioning should be aware of large macro cells and may result in bins with different sizes. During simulated annealing, different bin sizes have to be considered. The techniques discussed in this work can be easily incorporated into any hierarchical placement flow and effectively produce legal final layouts with a short runtime.
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Taghavi, T., Yang, X., Choi, BK., Wang, M., Sarrafzadeh, M. (2007). Congestion Minimization in Modern Placement Circuits. In: Nam, GJ., Cong, J. (eds) Modern Circuit Placement. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68739-1_6
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