Design Techniques for Current-Mode Circuits

Abstract

The rapid down-scale of the feature size of MOS devices, the aggressive reduction in the supply voltage, and the moderate reduction in the threshold voltage of modern CMOS technologies have greatly affected the performance of CMOS current-mode circuits, reflected by a small dynamic range, a reduced effective gate-source voltage, a low device output impedance, and an increased level of device mismatches. This chapter examines the design techniques that improve the performance of low-voltage CMOS current-mode circuits. The chapter is organized as follows : Section 2.1 examines the characteristics of basic current amplifiers. Section 2.2 investigates the techniques that boost the output impedance of current-mode circuits. Section 2.3 examines the techniques that lower the input impedance of current-mode circuits. Section 2.4 presents a balancing network approach for eliminating the mismatch-induced output offset current of current-mode circuits. In Section 2.5, an effective power reduction technique called current-branching is investigated. Section 2.6 introduces resistor series peaking, inductor series peaking, and current feedback for bandwidth improvement of current-mode circuits. Section 2.7 looks into circuit techniques for dynamic range improvement, specifically the characteristics of class AB current amplifiers.