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Design and Development of Stress-Engineered Compliant Interconnect for Microelectronic Packaging

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Abstract

Power and latency are fast becoming major bottlenecks in the design of high performance microprocessors and computers. Power relates to both consumption and dissipation, and therefore, effective power distribution design and thermal management solutions are required. Latency is caused by the global interconnects on the integrated circuit (IC) that span at least half a chip edge due to the resistance–capacitance (RC) and transmission line delay [1]. Limits to chip power dissipation and power density and limits on hyper-pipelining in microprocessors threaten to impede the exponential growth in microprocessor performance. In contrast, multicore processors can continue to provide a historical performance growth on most consumer and business applications provided that the power efficiency of the cores stays within reasonable power budgets. To sustain the dramatic performance growth, a rapid increase in the number of cores per die and a corresponding growth in off-chip bandwidth are required [2]. Thus, it is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) (21.1) that by the year 2018, with the IC node size shrinking to 22 nm by 2016 and 14 nm by 2020, the chip-to-substrate area-array input–output interconnects will require a pitch of 70 μm [3]. Furthermore, to reduce the RC and transmission line delay, low-K dielectric/Cu and ultra-low-K dielectric/Cu interconnects on silicon will become increasingly common. In such ICs, the thermo-mechanical stresses induced by the chip-to-substrate interconnects could crack or delaminate the dielectric material causing reliability problems.

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References

  1. Ho, R., Mai, K., and Horowitz, M., “The Future of Wires,” Proceedings of the IEEE, vol. 89, no. 4, pp. 490–504, 2001

    Google Scholar 

  2. Hofstee, H.P, “Future Microprocessors and Off-Chip SOP Interconnect,” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, pp. 301–303, 2004

    Article  Google Scholar 

  3. International Technology Roadmap for Semiconductor – 2002 Update, http://public.itrs.net/, 2002

  4. Lau, J.H. and Pao, Y.S., Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, New York: McGraw-Hill, ISBN 0-070-36648-9, 1996

    Google Scholar 

  5. Tummala, R.R, ed., Fundamentals of Microsystems Packaging, New York: McGraw-Hill, 2001

    Google Scholar 

  6. Viswanadham, P. and Singh, P., Failure Modes and Mechanisms in Electronic Packages, New York: Chapman & Hall, 1998

    Book  Google Scholar 

  7. Ghaffarian, R., “Chip-Scale Package Assembly Reliability,” Chip Scale Review, Nov 1998.

    Google Scholar 

  8. Chang, C.S., Oscilouski, A., and Bracken, R.C., “Future Challenges in Electronics packaging,” Circuits & Devices, vol. 14, no. 2, pp. 45–54, 1998

    Article  Google Scholar 

  9. Fjelstad, J., “The Evolution of Area Array Packaging from BGA to CSP,” Proceedings of SEMICON Europa, Geneva, Switzerland, April, 1998.

    Google Scholar 

  10. Fjelstad, J., “Wafer Level Packaging of Compliant CSPs Using Flexible Film Interposers,” HDI: The Magazine of High-Density Interconnect, April 1999

    Google Scholar 

  11. Kim, Y.G., Mohammed, I., Seol, B.S., Kang, T.G., “Wide Area Vertical Expansion (WAVE™) Package Design for High Speed Application: Reliability and Performance.” Proceedings of the 51th Electronic Components and Technology Conference (ECTC), 2001, pp. 54–62

    Google Scholar 

  12. Novitsky, J. and Miller, C., “MicroSpringTM Contacts on Silicon: Delivering Moore’s Law-type Scaling to Semiconductor Package, Test and Assembly”, Proceedings of 2000 HD International Conference on High-Density Interconnect and Systems Packaging (SPIE Vol. 4217), Colorado, USA, p. 250, 2000

    Google Scholar 

  13. Tracy, N.L., Rothenberger, R., Copper, C., Corman, N., Biddle, G., Mattews, A., McCarthy, S., “Array Sockets and Connects Using MicroSpringTM Technology,” 26th IEEE/CPMT International Electronics Manufacturing Technology Symposium, Oct 2000, pp. 129–140

    Google Scholar 

  14. Patel, C.S., Martin, K.P., Meindl, J.D., “Performance Issues in High-Density Printed Wiring Board Design for High I/O Compliant Wafer Level Packages,” 2nd Annual Semiconductor Packaging Technologies Symposium, July 1999

    Google Scholar 

  15. Bakir, M.S. Bakir, H.A. Reed, H.D. Thacker, P.A. Kohl, K.P. Martin, and J.D. Meindl. “Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI),” IEEE Transactions on Electron Devices, vol. 50, no. 10, October, 2003, pp. 2039–2048

    Google Scholar 

  16. Bakir, M.S., Reed, H.A., Kohl, P.A., Martin, K.P., and Meindl, J.D., “Sea of Leads Ultra High-Density Compliant Wafer-Level Packaging Technology”, Proceedings of 52nd Electronic Components and Technology Conference, San Deigo, CA, p. 1087, 2002

    Google Scholar 

  17. Zhu, Q., Ma, L., and Sitaraman, S.K., “Design and Fabrication of β-Helix – an Off-Chip Interconnect”, Proceedings of ASME International Mechanical Engineering Congress (ASME- IMECE), New Orlean, LA, 2002

    Google Scholar 

  18. Zhu, Q., Ma, L., and Sitaraman, S.K., “Design Optimization of One-Turn Helix – a Novel Compliant Off-Chip Interconnect,” IEEE Transactions on Advanced Packaging, vol. 26, no. 2, pp. 106–112, 2003

    Article  CAS  Google Scholar 

  19. Zhu, Q., Ma, L., and Sitaraman, S.K., “Development of G-Helix Structure as Off-Chip Interconnect,” Journal of Electronic Packaging, ASME Transactions, vol. 126, pp. 237–246, 2004

    Article  CAS  Google Scholar 

  20. Kacker, K., Sokol, T., and Sitaraman, S.K., “FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects,” Proceedings of 57th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Reno, NV, pp. 1678–1684, 2007

    Google Scholar 

  21. Smith, D.L. and Alimonda, A.S., “A New Flip Chip Technology for High-Density Packaging”, Proceedings of 46th Electronic Components and Technology Conference, pp. 1069, 1996

    Google Scholar 

  22. Ma, D.L.; Zhu, A. Q.; Sitaraman, S.; Chua, C. L.; Fork, D. K., “Compliant cantilevered spring interconnects for flip-chip packaging.” Proceedings of the 51st Electronic Components and Technology Conference, May 29-June 1, 2001, Orlando, FL., pp. 761–766

    Google Scholar 

  23. Hoffman, D.W. and Thornton, J.A., “Internal Stresses in Cr, Mo, Ta and Pt Films Deposited by Sputtering from a Planar Magnetron Source”, Journal of Vacuum Science Technology, vol. 20, no. 3, p. 355, 1982

    Article  CAS  Google Scholar 

  24. Windischmann, H., “Intrinsic Stress in Sputter-Deposited Thin Films”, Critical Reviews in Solid State and Material Sciences, vol. 17, no. 6, p. 547, 1992

    Article  Google Scholar 

  25. Ma et al. (2004)

    Google Scholar 

  26. Chua, C.L., Fork, D.K., and Hantschel, T., “Densely Packed Optoelectronic Interconnect Using Micromachined Springs”, IEEE Photonics Technology Letters, vol. 14, no. 6, p. 846, 2002

    Article  Google Scholar 

  27. JESD22-A104-B, “JEDEC Standard – Temperature Cycling”, JEDEC Solid State Technology Association, Electronic Industries Alliance, July, 2000

    Google Scholar 

  28. Pascoe, K.J., Properties of Materials for Electrical Engineers, New York: Wiley, ISBN 0–471–66911–3, p. 163, 1973

    Google Scholar 

  29. Klein, K.M., Zheng, J., Gewirtz, A., Sarma, D.S.R., Rajalakshmi, S., and Sitaraman, S.K., “Array of Nano-Cantilevers as a Bio-Assay for Cancer Diagnosis,” Proceedings of 55th Electronic Components and Technology Conference, IEEE-CPMT and EIA, Orlando, FL, pp. 583–587, 2005

    Google Scholar 

  30. Klein, K.M. and S.K. Sitaraman. “Compliant stress-engineered interconnects for next generation packaging,” Proceedings of the ASME International Mechanical Engineering Congress and Exposition, Anaheim, CA, November 13–19, 2004, IMECE2004-61990

    Google Scholar 

Unused references

  • Archard, J.F., “Contact and Rubbing of Flat Surfaces ”, Journal of Applied Physics, vol. 24, no. 8, p. 981, 1953

    Article  Google Scholar 

  • Akyuz, F.A. and Merwin, J.E., “Solution of Nonlinear Problems of lastoplasticity by Finite Element Method ”, AIAA Journal, vol. 6, p. 1825, 1968

    Article  Google Scholar 

  • Antler, M., “Sliding Wear of Metallic Contacts”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. CHMT-4, no. 1, p. 15, 1981

    Article  CAS  Google Scholar 

  • Barber, J.R. and Ciavarella, M., “Contact Mechanics”, International Journal of Solids and Structures, vol. 37, p. 29, 2000

    Article  Google Scholar 

  • Begley, M.R. and Hutchinson, J.W., “Plasticity in Fretting of Coated Substrates”, Engineering Fracture Mechanics, vol. 62, p. 145, 1999

    Article  Google Scholar 

  • Campbell, D.S., “Mechanical Properties of Thin Films”, in Handbook of Thin Film Technology, Edited by Maissel, L.I. and Glang, R., New York: McGraw-Hill, p. 12, 1970

    Google Scholar 

  • CINDAS Micrelectronics Packaging Materials Database (version 2.21), Center of Information and Numerical Data Analysis and Synthesis, Purdue Univeristy, 1999

    Google Scholar 

  • Challen, J.M., Oxley, P.L.B., and Hockenhull, B.S., “Prediction of Archard’s Wear Coefficient for Metallic Sliding Friction Assuming A Low Cycle Fatigue Wear Mechanism”, Wear, vol. 111, p.275, 1986

    Article  Google Scholar 

  • Chen, J., http://chenjian.virtualave.net/packaging/, 2003

  • Chidambaram, N.V., “A Numerical and Experimental Study of Temperature Cycle Wire Bond Failure”, Proceedings of 41st Electronic Components Technology Conference, Atlanta, GA, p. 877, 1991

    Google Scholar 

  • Cuomo, J.J., Harper, J.M.E., Garnieri, C.R., Yee, D.S., Attansio, L.J., Wu, C.T., and Hammond, R.H., “Modification of Niobium Film Stress by Low Energy Ion Bombardment During Deposition”, Journal of Vacuum Science Technology, vol. 20, p.349, 1982

    Article  CAS  Google Scholar 

  • Dais, J.L. and Howland, F.L., “Fatigue Failure of Encapsulated Gold-Beam Lead and TAB Devices”, IEEE Transaction on Components, Hybrids and Manufacturing Technology, vol. CHMT-1, no. 2, p. 158, 1978

    Article  Google Scholar 

  • D’Heurle, F.M., “Aluminum Films Deposited by RF Sputtering” Metallurgy Transaction, vol. 1, p. 725, 1970

    Article  Google Scholar 

  • Dumas, G. and Baronet, C.N., “Elasto-plastic Indentation of a Half-space by a Long Rigid Cylinder”, International Journal of Mechanical Sciences, vol. 13, p. 519, 1971

    Article  Google Scholar 

  • Emory, R., Emory, R., “Mechanical and Electrical Considerations of Compliant Interconnect”, Internal Project Report, Intel Corporation, 2001

    Google Scholar 

  • Finegan, J.D. and Hoffman, R.W., “Stress and Stress Anisotropy in Evaporated Iron Films”, Journal of Applied Physics, vol. 30, p. 597, 1959

    Article  CAS  Google Scholar 

  • Gere, J.M. and Timoshenko, S.P., Mechanics of Materials, Third Edition, Boston: PWS, 1990

    Google Scholar 

  • Giannakopoulos, A.E. and Larsson, P.L., “Analysis of Pyramid Indentation of Pressure-sensitive Hard Metals and Ceramics”, Mechanics of Materials, vol. 25, p. 1, 1997

    Article  Google Scholar 

  • Giannakopoulos, A.E. and Suresh, S., “A Three-dimensional Analysis of Fretting Fatigue”, Acta Materialia, vol. 46, no. 1, p. 177, 1998

    Article  CAS  Google Scholar 

  • Grover, F. W., “Inductance Calculations – Working Formulas and Tables”, New York: D. Van Nostrand, p. 164, 1980

    Google Scholar 

  • Hardy, C., Barnet, C.N., and Tordion, G.V., “Elastoplastic Indentation of a Half-space By a Rigid Sphere”, Journal of Numerical Methods in Engineering, vol. 3, p. 451, 1971

    Article  Google Scholar 

  • Harper, J.M.E., Cabral Jr., C., Andricacos, P.C., Gignac, L., Noyan, I.C., Rodbell, K.P., and Hu, C.K., “Mechanisms for Microstructure Evolution in Electroplated Copper Thin Films Near Room Temperature,” Journal of Applied Physics, vol. 86, no. 5, pp. 2516–2525, 1999

    Article  CAS  Google Scholar 

  • Hertz, H., “On the Contact of Elastic Solids”, J. Reine und Angew. Math., vol. 92, p. 156, 1882, (in German)

    Google Scholar 

  • Hills, D.A., Nowell, D., and Sackfield, A., Mechanics of Elastic Contacts, Oxford: Butterworth-Heinemann, ISBN 0–750–60540–5, 1993

    Google Scholar 

  • Hoffmanm R.W., “The Mechanical Properties of Nonmetallic Thin Films”, in Physics of Non-Metallic Thin Films, NATO Advanced Study Institute Series, Edited by Dupuy, C.H. and Cachard, A., vol. B-14, New York: Plenum, p. 273, 1976

    Google Scholar 

  • Hoffman, D.W. and Gaerttner, M.R., “Modification of Evaporated Chromium by Concurrent Ion Bombardment”, Journal of Vacuum Science Technology, vol. 17, p.425, 1980

    Article  CAS  Google Scholar 

  • Iscoff, R., “Demands For Higher Speed and Greater Accuracy Are Driving the Die Placement Equipment Market”, Chip Scale Review, Jan–Feb, 2001

    Google Scholar 

  • Johnson, K.L., Contact Mechanics, U.K.: Cambridge University Press, ISBN 0-521-34796-3, 1985

    Google Scholar 

  • Kapoor, A., “A Re-evaluation of the Life to Rupture of Ductile Metals By Cyclic Plastic Strain”, Fatigue Fracture Engineering Material Structure, vol. 17, no. 2, p. 201, 1994

    Article  CAS  Google Scholar 

  • Kasap, S.O., Principles of Electronic Materials and Devices, Second Edition, New York: McGraw-Hill, ISBN 0-072-45636-1, p. 111, 2001

    Google Scholar 

  • Kim, W., Madhavan, R., Mao, J., Choi, J., Choi, S., Ravi, D., Sundaram, V., Sankararaman, S., Gupta, P., Zhang, Z., Lo, G., Swaminathan, M., Tummala, R., Sitaraman, S., Wong, C.P., Iyer, M., Rotaru, M., and Tay, A., “Electrical Design of Wafer Level Package on Board for Gigabit Data Transmission,” Proceedings of Electronics Packaging and Technology Conference, Singapore, pp. 150–159, 2003.

    Google Scholar 

  • Kragelsky, I.V., Friction and Wear, London: Butterworths, 1965

    Google Scholar 

  • Lau, J.H., Flip Chip Technologies, New York: McGraw-Hill, ISBN 0-07-036609-8, 1995

    Google Scholar 

  • Lau, J.H., ed., Flip Chip Technologies, New York: McGraw-Hill, 1996.

    Google Scholar 

  • Lau, J.H., Rice D.W., and Avery, P.A., “Elastoplastic Analysis of Surface-Mount Solder Joints”, IEEE Transaction on Components, Hybrids and Manufacturing Technology, vol. CHMT-10, no. 3, p. 346, 1987

    Article  Google Scholar 

  • Lau, J.H., Rice, D.W., and Harkins, C.G., “Thermal Stress Analysis of Tape Automated Bonding Packages and Interconnections”, IEEE Transaction on Components, Hybrids and Manufacturing Technology, vol. CHMT-13, no. 1, p. 182, 1990

    Article  Google Scholar 

  • Lau, J.H. and Lee, S.W.R., “Reliability of 96.5Sn-3.5Ag Lead-Free Solder-Bumped Wafer Level Chip Scale Package (WLCSP) on Build-Up Microvia Printed Circuit Board”, Proceedings of 2001 International Conference on High-Density Interconnect and System Packaging, Santa Clara, CA, p. 314, 2001.

    Google Scholar 

  • Lee, C.H., Masaki, S., and Kobayashi, S., “Analysis of Ball Indentation”, International Journal of Mechanical Sciences, vol. 14, p. 417, 1972

    Article  Google Scholar 

  • Li, D.L., Light, D., Castillo, D., Beroz, M., Nguyen, M., and Wang, T., “A Wide Area Vertical Expansion (WAVETM) Packaging Process Development”, Proceedings of 51st Electronic Components and Technology Conference, Lake Buena Vista, FL, p. 367, 2000

    Google Scholar 

  • Lingk, C., Gross, M.E., and Brown, W.L., “Texture development of blanket electroplated copper films,” Journal of Applied Physics, vol. 87, no. 5, pp. 2232–2236, 2000

    Article  CAS  Google Scholar 

  • Loctite Corporation, “Product 3335 – Technical Data Sheet”, Nov 2000

    Google Scholar 

  • Material Database of MEMSnet, http://www.memsnet.org/material/, 2003

  • Meyers, R.H. and Montgomery, D.C., Response Surface Methodology: Process and Product Optimization Using Designed Experiments, New York: Wiley, 1995

    Google Scholar 

  • Modi, M., “Fracture in Stress-Engineered, High Density, Thin Film Interconnects”, Ph.D. Dissertation, Woodruff School of Mechanical Engineering, Georgia Institute of Technology, 2003

    Google Scholar 

  • Muskhelishvili, N.I., Singular Integral Equations, Boundary Problems of Function Theory and their Application to Mathematical Physics, Gronigen: Noordhoff, 1953

    Google Scholar 

  • Nordic Electronics Packaging Guideline, http://extra.ivf.se/ngl/, developed by Danish Electronics, Lights and Acoustics (DELTA), IVF – Swedish Institute of Production Engineering Research, SINTEF – Norway, VTT – Technical Research Center of Finland

  • Pan, T., “Thermal Cycling Induced Plastic Deformation in Solder Joints I: Accumulated Deformation in Surface Mount Joints”, Transactions of the ASME. Journal of Electronic Packaging vol. 113, no. 1, p. 8, 1991

    Article  Google Scholar 

  • Pan, T., “Thermal Cycling Induced Plastic Deformation in Solder Joints I: Accumulated Deformation in Through-hole Joints”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, vol. 14, no. 4, p. 824, 1991

    Article  Google Scholar 

  • Pang, J.H.L. and Tan, C.K., “Thermal Analysis of a Wire Bond Chip-On-Board Package”, ITherm’98, The Sixth InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, Seattle, Washington, p. 481, 1998

    Google Scholar 

  • Perez-Prado, M.T. and Vlassak, J.J., “Microstructural evolution in electroplated Cu thin films,” Scripta Materialia, vol. 47, no. 12, pp. 817–823, 2002

    Article  CAS  Google Scholar 

  • Qin, I.W., “Wire Bonding: The Preferred Interconnect Method”, Chip Scale Review, Nov–Dec, 2002

    Google Scholar 

  • Rabinowicz, E., “The Least Wear”, Wear, vol. 100, p. 533, 1984

    Article  Google Scholar 

  • Semiconductor Industry Association, International Technology Roadmap for Semiconductors: Assembly and Packaging, 2005.

    Google Scholar 

  • Skalski, K., “Contact Problem Analysis of an Elastoplastic Body”, Prace Naukowe Mechanica, z. 67, Warsaw Polytechnic, 1979

    Google Scholar 

  • Smith, L.D., Anderson, R.E., Forehand, D.W., Pelc, T.J., and Roy, T., “Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology,” IEEE Transactions on Advanced Packaging, vol. 22, pp. 284–291, 1999

    Article  Google Scholar 

  • Suresh, S., Fatigue of Materials, Second Edition, U.K.: Cambridge University Press, ISBN 0-521-57847-7, 2001

    Google Scholar 

  • Swaminathan, M., Kim, J., Novak, I., and Libous, J., “Power Distribution Networks for System on a Package: Status and Challenges,” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, pp. 286–300, 2004

    Article  Google Scholar 

  • Syed, A.R. and Doty, M., “Are We Over Designing for Solder Joint Reliability? Field vs. Accelerated Conditions, Realistic vs. Specified Requirements”, Proceedings of 49th Electronic Components and Technology Conference, San Diego, CA, p. 111, 1999

    Google Scholar 

  • Tian, H., Saka, N. and Rabinowicz, E., “Friction and Failure of Electroplated Sliding Contacts”, Wear, vol. 142, p. 57, 1991

    Article  CAS  Google Scholar 

  • Timoshenko, S. and Goodier, J.N., Theory of Elasticity, Third Edition, New York: McGraw-Hill, 1951

    Google Scholar 

  • Torrance, A.A. and Buckley, T.R., “A Slip-line Field Model of Abrasive Wear”, Wear, vol. 196, p. 35, 1996

    Article  CAS  Google Scholar 

  • Truman, C.E., Sackfield, A. and Hill, D.A., “Contact Mechanics of Wedge and Cone Indenters”, International Journal of Mechanics Science, vol. 37, no. 3, p. 261, 1995

    Article  Google Scholar 

  • Tummala, R.R., Fundamentals of Microelectronic Packaging, New York: McGraw-Hill, ISBN 0–071–37169–9, 2001

    Google Scholar 

  • Tummala, R.R., Orientation Presentation at Industrial Advisory Board Meeting, Georgia Institute of Technology – Packaging Research Center, 2003

    Google Scholar 

  • Tummala, R.R, “Special Issues on System on a Package (SOP),” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, 2004.

    Google Scholar 

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Authors and Affiliations

  1. Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab, The George W. Woodruff School of Mechanical Engineering, Georgia Institute of Technology, 813 Ferst Drive, Atlanta, GA, 30332-0405, USA

    Lunyu Ma, Suresh K. Sitaraman, Qi Zhu & Kevin Klein

  2. Palo Alto Research Center, 3333 Coyote Hill Rd., Palo Alto, CA, 94304, USA

    David Fork

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  1. Lunyu Ma
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  2. Suresh K. Sitaraman
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  3. Qi Zhu
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  4. Kevin Klein
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Correspondence to Suresh K. Sitaraman .

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  1. Dept. Electrical &, Computer Engineering, Portland State University, Portland, Oregon, USA

    James E. Morris

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Ma, L., Sitaraman, S.K., Zhu, Q., Klein, K., Fork, D. (2008). Design and Development of Stress-Engineered Compliant Interconnect for Microelectronic Packaging. In: Morris, J. (eds) Nanopackaging. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-47325-3_21

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