Abstract
Packaging materials undergo dimensional changes under environmental exposure to temperature change. Thermomechanical cyclic loads induce stresses and damage interconnects. Underfills compensate for the mismatch in coefficient of thermal expansion (CTE) between silicon and the printed circuit board (PCB), and have been used as a supplemental restraint mechanism to enhance the reliability for flip-chip devices and chip-scale packages in a wide variety of applications including portable consumer electronics such as cellular phones, laptops, under-the-hood electronics, microwave applications, system in package (SIP), high-end workstations, and several other high-performance applications. Figure 14.1 shows an underfilled flip-chip assembly, with solder interconnects between the silicon chip and the PCB. It surrounds the solder balls. Underfill technology has evolved to meet the demand of decreasing feature size and increasing input/output (I/O) number in the integrated circuit (IC) chip.
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Lall, P., Islam, S., Tian, G., Suhling, J., Shinde, D. (2008). Nano-Underfills for Fine-Pitch Electronics. In: Morris, J. (eds) Nanopackaging. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-47325-3_14
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DOI: https://doi.org/10.1007/978-0-387-47325-3_14
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