Metric-Driven Methodology Speeds the Verification of a Complex Network Processor

In my business unit, we often struggle to keep our hardware in sync with the software schedule. Doing so requires a great deal of resources. So it was no small feat when the verification flow for one of our recent designs, the Programmable IP Services Accelerator (PISA) FPGA in development, was completed ahead of schedule and well before the system software was delivered. In fact, it’s unprecedented and has really turned some heads within our various groups.