Architectural Designs For the Advanced Encryption Standard

Part of the Signals and Communication Technology book series (SCT)


In this chapter we present some of the most common architectural alternatives to implement Advanced Encryption Standard (AES) in reconfigurable hardware. The first factor to be considered on implementing AES is the application. There are high speed applications like High Definition TV (HDTV) and video conferencing where high performance is required. The target throughput, expressed in gigabits per second (Gbps), must be specified, and to achieve such a high performance we can replicate several functional units to increase parallelism. That would however imply higher power and hardware area requirements.


Clock Cycle Advance Encryption Stan Composite Field Pipeline Architecture Advance Encryption Stan Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2006

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