Abstract
Tomorrow’s pocket devices will all have Internet-based communication capabilities. The advent of mobile phones, PDAs (Pocket Data Assistant) and pocketPC’s joint to the newcomer’s third generation wireless networks such as UMTS will soon allow everyone to be connected, everywhere. In this competitive marketplace where many similar products compete for the consumer attention, performances level is a very important criterion.Videoconferencing, digital music broadcast, speech recognition are a few example of the new features allowed by the new third generation networks. This kind of multimedia, data oriented content requires highly efficient architectures; and nowadays mobile system-on-chip solution will no longer be able to deal with the critical constraints like area, power, and data computing efficiency. In this paper we will propose a new dynamically reconfigurable network, dedicated to data oriented applications such as the one targeted on third generation networks. Principles, realisations and comparative results will be exposed for some classical applications, targeted on different architectures.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35597-9_40
Chapter PDF
Similar content being viewed by others
References
Stephen Brown and J. Rose, “Architecture of FPGAs and CPLDs: A Tutorial,” IEEE Design and Test of Computers, Vol. 13, No. 2, pp. 42–57, 1996.
Why reconfigurable computing, Department of Computer Science, Computer Structures Group, http://xputers.informatik.uni-k1.de/.
R. Hartenstein, H. Grünbacher (Editors): The Roadmap to Reconfigurable computing Proc.FPL2000, Aug.27–30,2000;LNCS,Springer-Verlag2000.
J. R. Hauser and J. Wawrzynek, “Garp: A MIPS Processor with a Re-configurable Coprocessor,” Proc. of the IEEE Symposium on FPGAs for Custom Computing Machines, 1997.
A. Abnous, C. Christensen, J. Gray, J. Lenell, A. Naylor and N. Bagherzadeh, “ Design and Implementation of the Tiny RISC microprocessor,” Microprocessors and Microsystems, Vol. 16, No. 4, pp. 187–94, 1992.
C. Hsieh and T. Lin, “ VLSI Architecture For Block-Matching Motion Estimation Algorithm,” IEEE Trans. on Circuits and Systems for Video Technology, vol. 2, pp. 169–175, June 1992.
N. Ahmed, T. Natarajan, and K.R. Rao, “Discrete cosine transform,” IEEE Trans. On Computers, vol. C-23, pp. 90–93, Jan 1974.
ISO/IEC JTC1 CD 10918. Digital compression and coding of continuous-tone still images — part 1, requirements and guidelines, ISO, 1993 ( JPEG).
ISO/IEC JTC1 CD 13818. Generic coding of moving pictures and associated audio: video, ISO, 1994 (MPEG-2 standard).
High Productivity Computing Systems (HPCS), Defense and Advanced Research Projects Agency, http://www.darpa.mil/ito/research/hpcs/index.html.
Xilinx, the Programmable Logic Data Book, 1994
A.Bugeja and W. Yang, “A Re-configurable VLSI Coprocessing System for the Block Matching Algorithm”, IEEE Trans. On VLSI systems, vol. 5, September 1997.
Intel Application Notes for Pentium MMX, http://developer.intel.com/.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 IFIP International Federation for Information Processing
About this chapter
Cite this chapter
Sassatelli, G., Torres, L., Benoit, P., Cambon, G., Robert, M., Galy, J. (2002). Dynamically Reconfigurable Architectures for Digital Signal Processing Applications. In: Robert, M., Rouzeyre, B., Piguet, C., Flottes, ML. (eds) SOC Design Methodologies. IFIP — The International Federation for Information Processing, vol 90. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35597-9_6
Download citation
DOI: https://doi.org/10.1007/978-0-387-35597-9_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-6530-4
Online ISBN: 978-0-387-35597-9
eBook Packages: Springer Book Archive