Hardware Implementation of Concurrent Periodic EFSMs

  • Hisaaki Katagiri
  • Masayuki Kirimura
  • Keiichi Yasumoto
  • Teruo Higashino
  • Kenichi Taniguchi
Part of the IFIP — The International Federation for Information Processing book series (IFIPAICT, volume 55)


This paper proposes a concurrent periodic EFSMs model and a technique to synthesize hardware circuits from real-time system specifications in this model. In the proposed model, the data exchange by synchronous execution of the same events in multiple EFSMs (multi-way synchronization) can be specified like LOTOS. The executable time range of each event can be specified as a logical conjunction of linear inequalities of the execution time of its preceding events, constants and integer variables with some values input from environments. Here, we assume that every event sequence starting from the initial state in each EFSM returns to the initial state in the specified time interval. The proposed synthesis technique implements only executable combination of branches in a given specification with a schedule table which guarantees that if each I/O event is executed within the specified time range, at least one of the following event sequences remains executable. Some experiments show that the performance and size of the generated circuits are reasonable for practical use.


Real-time systems hardware implementation scheduling multi-way synchronization E-LOTOS 


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Copyright information

© IFIP International Federation for Information Processing 2000

Authors and Affiliations

  • Hisaaki Katagiri
    • 1
  • Masayuki Kirimura
    • 1
  • Keiichi Yasumoto
    • 2
  • Teruo Higashino
    • 1
  • Kenichi Taniguchi
    • 1
  1. 1.Graduate School of Eng. Sci.Osaka Univ.Toyonaka, OsakaJapan
  2. 2.Dept. Info. Proc. & Man.Shiga Univ.Hikone, ShigaJapan

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