Abstract
This paper presents a high-level clock distribution strategy for usage in a design-and-reuse environment. This strategy allows for controlled clock distribution across an arbitrary number of blocks through the usage of controlled delay lines. A new clock frequency multiplication structure optimised for this clock distribution strategy is finally proposed, since multifrequency clock support is highly desired.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35498-9_57
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© 2000 IFIP International Federation for Information Processing
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Aguiar, R.L., Santos, D.M. (2000). Clock Distribution Strategy for IP-based Development. In: Silveira, L.M., Devadas, S., Reis, R. (eds) VLSI: Systems on a Chip. IFIP — The International Federation for Information Processing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35498-9_17
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DOI: https://doi.org/10.1007/978-0-387-35498-9_17
Publisher Name: Springer, Boston, MA
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